INTEGRATED PASSIVE MODULE, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20160150649A1
• Filed: 11/25/2015
• Published: 05/26/2016
• Est. Priority Date: 11/25/2014
• Status: Abandoned Application

• Current Assignee: Hsien-Ping Peng
• Original Assignee: Hsien-Ping Peng
• Inventors: PENG, Hsien-Ping
• Application Number:
  US14/952,571
• Publication Number:
  US 20160150649A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates

Abstract

An integrated passive module comprises a ceramic substrate, a planar layer and a thin film laminate. At least one first passive component is embedded in ceramic substrate. The planar layer is disposed on the ceramic substrate. The thin film laminate comprises at least one second passive component and disposed on the planar layer. The thin film laminate is electrically connected to the first passive component. This disclosure also discloses a semiconductor device comprising an integrated passive module and at least one active component. The at least one active component is electrically connected to the first passive component and the second passive component.

Claims

1. An integrated passive module, comprising:

a ceramic substrate in which at least one first passive component is embedded;

a planar layer disposed on the ceramic substrate; and

a thin film laminate comprising at least one second passive component and disposed on the planar layer, wherein the thin film laminate is electrically connected to the first passive component.

2. The integrated passive module of claim 1, wherein the first passive component includes a capacitor, an inductor or a varistor.

3. The integrated passive module of claim 2, wherein the capacitance of the capacitor is smaller than or equal to 100 nF, and the inductance of the inductor is greater than or equal to 1 nH.

4. The integrated passive module of claim 1, wherein the ceramic substrate further comprises a plurality of electric connection portions, the electric connection portions are exposed from the outer surface of the ceramic substrate, and some electric connection portions are electrically connected to the first passive component.

5. The integrated passive module of claim 1, wherein the second passive component is disposed on the planar layer.

6. The integrated passive module of claim 1, wherein the planar layer has a conduction pattern, and the conduction pattern is electrically connected to the first passive component and the second passive component.

7. The integrated passive module of claim 1, wherein the second passive component includes a capacitor, an inductor or a resistor.

8. The integrated passive module of claim 7, wherein the capacitance of the capacitor is smaller than or equal to 20 pF, and the inductance of the inductor is smaller than or equal to 50 nH.

9. The integrated passive module of claim 1, wherein the material of the planar layer includes Polyimide, Benzocyclobutene, or solder mask.

10. A semiconductor device, comprising:

an integrated passive module comprising;

a ceramic substrate in which at least one first passive component is embedded;

a planar layer disposed on the ceramic substrate; and

a thin film laminate disposed on the planar layer and electrically connected to the first passive component, wherein the thin film laminate comprises at least one second passive component; and

at least one active component electrically connected to the first passive component and the second passive component.

11. The semiconductor device of claim 10, wherein the active component is disposed on one side of the thin film laminate facing away from the ceramic substrate.

12. The semiconductor device of claim 10, further comprising:

a circuit layout layer disposed between the thin film laminate and the active component, wherein the active component is electrically connected to the first passive component through the circuit layout layer and the thin film laminate.

13. A method for manufacturing semiconductor device, comprising:

providing a ceramic substrate in which at least one first passive component is embedded;

grinding a surface of the ceramic substrate;

forming a planar layer on the surface of the ceramic substrate; and

forming a thin film laminate on one side of the planar layer facing away from the ceramic substrate, wherein the thin film laminate comprises at least one second passive component, and the thin film laminate is electrically connected to the first passive component.

14. The method of claim 13, wherein the ceramic substrate is formed by sintering.

15. The method of claim 13, wherein in the grinding, the thickness of the ceramic substrate is reduced by 5-10 μ

m with grinding.

16. The method of claim 13, wherein the first passive component embedded in the ceramic substrate is formed by thick film process.

17. The method of claim 13, wherein the planar layer is formed by lithography process, and the surface roughness (Ra) of the planar layer is smaller than or equal to 150 Å

.

18. The method of claim 13, further comprising:

disposing an active component on one side of the thin film laminate facing away from the ceramic substrate, wherein the active component is electrically connected to the first passive component and the second passive component.

19. The method of claim 18, further comprising:

before disposing the active component, forming a circuit layout layer on the side of the thin film laminate facing away from the ceramic substrate, wherein the active component is electrically to the first passive component through the circuit layout layer and the thin film laminate.