METHODS AND APPARATUS FOR MEASURING ANALYTES USING LARGE SCALE FET ARRAYS

• US 20160178570A1
• Filed: 12/16/2015
• Published: 06/23/2016
• Est. Priority Date: 12/18/2014
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: FIFE, Keith G.
• Granted Patent: US 10,379,079 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82

Abstract

A semiconductor device, comprising a first field effect transistor (FET) connected in series to a second FET, and a third FET connected in series to the first FET and the second FET. The semiconductor device further includes bias circuitry coupled to the first FET and the second FET, and an output conductor coupled to a terminal of the second FET, wherein the output conductor obtains an output signal from the second FET that is independent of the first FET.

Claims

1. A semiconductor device, comprising:

a first field effect transistor (FET) connected in series to a second FET;

a third FET connected in series to the first FET and the second FET;

bias circuitry coupled to the first FET and the second FET; and

an output conductor coupled to a terminal of the second FET, wherein the output conductor obtains an output signal from the second FET that is independent of the first FET.

2. The device of claim 1, wherein the third FET concurrently couples the first FET and the second FET to the output conductor in response to a select signal.

3. The device of claim 1, wherein the output signal from the second FET is independent of a voltage on a terminal of the first FET.

4. The device of claim 1, wherein the second FET comprises a source follower.

5. The device of claim 1, wherein the bias circuitry comprises at least one voltage source and at least one current sink.

6. The device of claim 1, wherein the bias circuitry applies a voltage source to the first FET and applies a current sink to the second FET.

7. The device of claim 1, wherein the output signal is dependent on the threshold voltage of the second FET.

8. The device of claim 1, wherein the first FET is operating under drain induced barrier lowering constraints when the output signal is obtained from the second FET.

9. The device of claim 1, wherein the first FET is operating under punch through mode constraints when the output signal is obtained from the second FET.

10. The device of claim 1, wherein the third FET is biased in at least one of a triode region and a saturation region, and the first FET is biased at a high fixed potential to induce drain induced barrier lowering in the first FET.

11. The device of claim 1, wherein the first and second FETs are coupled to respective first and second electrodes.

12. The device of claim 1, wherein the second FET is a chemically-sensitive field effect transistor (chemFET).

13. The device of claim 12, wherein the output signal is based on a hydrolysis event.

14. The device of claim 12, wherein the output signal relates to a nucleotide incorporation event detected by the second FET.

15. The device of claim 1, wherein the second FET is coupled to an electrode.

16. The device of claim 15, wherein the second FET is coupled to the electrode via a floating gate.

17. The device of claim 15, wherein the electrode is sensitive to ions.

18. The device of claim 15, further comprising a reaction site proximate to the electrode.

19. The device of claim 18, wherein the reaction site is coupled to the second FET via the electrode.

20. The device of claim 18, wherein the output signal indicates a chemical reaction occurring within the reaction site.