ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE

• US 20160190161A1
• Filed: 07/13/2015
• Published: 06/30/2016
• Est. Priority Date: 12/29/2014
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectric Technology Co. Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Company Limited
• Inventors: Liu, Liping, Han, Junqi, Ai, Yu
• Granted Patent: US 9,825,062 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/136259 Repairing; Defects
• CPC Class Codes: G02F 1/136263 Line defects
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1296 adapted to increase the uniformity of device parameters

Abstract

The present disclosure provides an array substrate and a method of manufacturing the same, and a display device comprising the array substrate. The array substrate comprises: a substrate; gate lines and data lines arranged to intersect one another on the substrate; a gate line connection conducting wire layer provided between the gate lines and the substrate and below the gate lines; and /or, a data line connection conducting wire layer provided in regions of the array substrate corresponding to the data lines; wherein the gate line connection conducting wire layer is electrically isolated from the data line connection conducting wire layer.

Claims

1. An array substrate, comprising a substrate, and gate lines and data lines arranged to intersect one another on the substrate, wherein the array substrate further comprises:

a gate line connection conducting wire layer provided between the gate lines and the substrate and below the gate lines; and

a data line connection conducting wire layer provided in regions of the array substrate corresponding to the data lines;

wherein the gate line connection conducting wire layer is electrically isolated from the data line connection conducting wire layer.

2. The array substrate according to claim 1, wherein

pixel electrode regions are delimited between the gate lines and the data lines, and

the gate line connection conducting wire layer is located directly under the gate lines, directly contacts and is connected with the gate lines, and is spaced away from the pixel electrode regions.

3. The array substrate according to claim 1, wherein the data line connection conducting wire layer is located below the data lines.

4. The array substrate according to claim 3, wherein

pixel electrode regions are delimited between the gate lines and the data lines,

the array substrate further comprises a gate insulation layer,

the data line connection conducting wire layer is located directly below the data lines, and

the gate insulation layer is located between the data lines and the data line connection conducting wire layer.

5. The array substrate according to claim 4, wherein the data line connection conducting wire layer and the gate line connection conducting wire layer are provided in the same connection conducting wire layer.

6. The array substrate according to claim 1, wherein each of the data line connection conducting wire layer and the gate line connection conducting wire layer is an ITO conducting layer.

7. A display device comprising the array substrate according to claim 1.

8. The display device according to claim 7, wherein

pixel electrode regions are delimited between the gate lines and the data lines, and

the gate line connection conducting wire layer is located directly under the gate lines, directly contacts and is connected with the gate lines, and is spaced away from the pixel electrode regions.

9. The display device according to claim 7, wherein the data line connection conducting wire layer is located below the data lines.

10. The display device according to claim 9, wherein

pixel electrode regions are delimited between the gate lines and the data lines,

the array substrate further comprises a gate insulation layer,

the data line connection conducting wire layer is located directly below the data lines, and

the gate insulation layer is located between the data lines and the data line connection conducting wire layer.

11. The display device according to claim 10, wherein the data line connection conducting wire layer and the gate line connection conducting wire layer are provided in the same connection conducting wire layer.

12. A method of manufacturing an array substrate, comprising steps of:

forming a pattern of gate lines, and forming a pattern of a gate line connection conducting wire layer below the gate lines; and

forming a pattern of data lines, and forming a data line connection conducting wire layer in regions of the array substrate corresponding to the data lines;

wherein the gate line connection conducting wire layer is electrically isolated from the data line connection conducting wire layer.

13. The method of claim 12, wherein the data line connection conducting wire layer is located below the data lines.

14. The method of claim 12, wherein the step of forming a pattern of gate lines, and forming a pattern of a gate line connection conducting wire layer below the gate lines comprises:

depositing an ITO conducting layer and a gate metal layer sequentially on a substrate, and

processing the ITO conducting layer and the gate metal layer by performing a patterning process one time so as to form the pattern of the gate line connection conducting wire layer and the pattern of the gate lines, wherein the pattern of the gate line connection conducting wire layer is located below the pattern of the gate lines and corresponds to the pattern of the gate lines.

15. The method of claim 12, wherein in the step of forming a pattern of data lines, and forming a data line connection conducting wire layer in regions of the array substrate corresponding to the data lines, the data line connection conducting wire layer is formed below the data lines.

16. The method of claim 15, wherein the step of forming a pattern of data lines, and forming a data line connection conducting wire layer in regions of the array substrate corresponding to the data lines comprises:

depositing an ITO conducting layer on regions of the substrate corresponding to regions where the pattern of the data lines is to be provided, and processing the ITO conducting layer through a patterning process to form the pattern of the data line connection conducting wire layer;

depositing a gate insulation layer on the pattern of the data line connection conducting wire layer; and

depositing a data line metal layer, and processing the metal layer through a patterning process to form the pattern of the data lines.

17. An array substrate, comprising a substrate, and gate lines and data lines arranged to intersect one another on the substrate, wherein the array substrate further comprises:

a gate line connection conducting wire layer provided between the gate lines and the substrate and below the gate lines;

or

a data line connection conducting wire layer provided in regions of the array substrate corresponding to the data lines.