Array substrate with redundant gate and data line repair structures

• US 9,825,062 B2
• Filed: 07/13/2015
• Issued: 11/21/2017
• Est. Priority Date: 12/29/2014
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectric Technology Co. Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectric Technology Co. Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: Liu, Liping, Han, Junqi, Ai, Yu
• Primary Examiner(s): Sarkar, Asok K
• Assistant Examiner(s): WITHERS, GRANT S
• Application Number:
  US14/797,781
• Publication Number:
  US 20160190161A1
• Time in Patent Office: 862 Days
• CPC Class Codes: G02F 1/136259 Repairing; Defects
• CPC Class Codes: G02F 1/136263 Line defects
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1296 adapted to increase the uniformity of device parameters

Abstract

The present disclosure provides an array substrate and a method of manufacturing the same, and a display device comprising the array substrate. The array substrate comprises: a substrate; gate lines and data lines arranged to intersect one another on the substrate; a gate line connection conducting wire layer provided between the gate lines and the substrate and below the gate lines; and/or, a data line connection conducting wire layer provided in regions of the array substrate corresponding to the data lines; wherein the gate line connection conducting wire layer is electrically isolated from the data line connection conducting wire layer.

Claims

1. An array substrate, comprising a substrate, and gate lines and data lines arranged to intersect one another on the substrate, wherein the array substrate further comprises:

a gate line connection conducting wire layer provided between the gate lines and the substrate and below the gate lines, configured such that when any of the gate lines is broken, the broken gate lines can be conducted through the gate line connection conducing wire layer therebelow, thereby achieving reconnection of the gate lines;

a data line connection conducting wire layer provided in regions of the array substrate corresponding to the data lines; and

a gate insulation layer located between the data lines and the data line connection conducting wire layer, to completely electrically insulate the data lines from the data line connection conducting wire layer, such that only the gate insulation layer is directly between the data lines and the data line connection conducting wire layer;

wherein pixel electrode regions are delimited between the gate lines and the data lines,

wherein the gate line connection conducting wire layer is electrically isolated from the data line connection conducting wire layer; and

wherein when any of the data lines is broken, two disconnected ends of the broken data line and the data line connection conducting wire layer are bridgeable by a bonding wire, so that the broken data line is reconnected.

2. The array substrate according to claim 1, wherein

pixel electrode regions are delimited between the gate lines and the data lines, and

the gate line connection conducting wire layer is located directly under the gate lines, directly contacts and is connected with the gate lines, and is spaced away from the pixel electrode regions.

3. The array substrate according to claim 1, wherein the data line connection conducting wire layer is located below the data lines.

4. The array substrate according to claim 1, wherein the data line connection conducting wire layer and the gate line connection conducting wire layer are provided in the same connection conducting wire layer.

5. The array substrate according to claim 1, wherein each of the data line connection conducting wire layer and the gate line connection conducting wire layer is an ITO conducting layer.

6. A display device comprising the array substrate according to claim 1.

7. The display device according to claim 6, wherein

pixel electrode regions are delimited between the gate lines and the data lines, and

the gate line connection conducting wire layer is located directly under the gate lines, directly contacts and is connected with the gate lines, and is spaced away from the pixel electrode regions.

8. The display device according to claim 6, wherein the data line connection conducting wire layer is located below the data lines.

9. The display device according to claim 8, wherein

pixel electrode regions are delimited between the gate lines and the data lines,

the data line connection conducting wire layer is located directly below the data lines.

10. The display device according to claim 9, wherein the data line connection conducting wire layer and the gate line connection conducting wire layer are provided in the same connection conducting wire layer.

11. A method of manufacturing an array substrate, comprising steps of:

forming a substrate, and forming gate lines and data lines arranged to intersect one another on the substrate;

forming a gate line connection conducting wire layer between the gate lines and the substrate and below the gate lines, such that when any of the gate lines are broken, the broken gate lines can be conducted through the gate line connection conducting wire layer therebelow, thereby achieving reconnection of the gate lines;

forming a data line connection conducting wire layer in regions of the array substrate corresponding to the data lines; and

forming a gate insulation layer located between the data lines and the data line connection conducting wire layer, to completely electrically insulate the data lines from the data line connection conducting wire layer, such that only the gate insulating layer is directly between the data lines and the data line connection conducting wire layer,

wherein pixel electrode regions are delimited between the gate lines and the data lines,

wherein the gate line connection conducting wire layer is electrically isolated from the data line connection conducting wire layer; and

wherein when any of the data lines is broken, two disconnected ends of the broken data line and the data line connection conducting wire layer area bridgeable by a bonding wire, so that the broken data line is reconnected.

12. The method of claim 11, wherein the data line connection conducting wire layer is located below the data lines.

13. The method of claim 11, wherein the step of forming a gate line connection conducing wire layer between the gate lines and the substrate and below the gate lines comprises:

depositing an ITO conducting layer and a gate metal layer sequentially on the substrate, and

processing the ITO conducting layer and the gate metal layer by performing a patterning process one time so as to form the gate line connection conducting wire layer and the gate lines, wherein the gate line connection conducting wire layer is located below the gate lines and corresponds to the gate lines.

14. The method of claim 11, wherein in the step of forming a data line connection conducting wire layer in regions of the array substrate corresponding to the data lines, the data line connection conducting wire layer is formed below the data lines.

15. The method of claim 14, wherein the step of forming a data line connection conducting wire layer in regions of the array substrate corresponding to the data lines comprises:

depositing an ITO conducting layer on regions of the substrate corresponding to regions where the data lines is to be provided, and processing the ITO conducting layer through a patterning process to form the data line connection conducting wire layer;

depositing the gate insulation layer on the data line connection conducting wire layer; and

depositing a data line metal layer, and processing the metal layer through a patterning process to form the data lines.