AUDIO PROCESSING SYSTEM
First Claim
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1. An audio processing system comprising:
- a storage domain including a system memory unit;
a first unit including a central processing unit (CPU) and a top domain, wherein the CPU decodes audio data stored in the storage domain to generate decoded audio data that is stored in the system memory unit;
a power management unit configured to provide at least one power supply signal to the first unit and the system memory unit; and
an audio sub-system including;
an audio buffer that stores decoded audio data received from the system memory unit,a first Direct Memory Access (DMA) unit that moves decoded audio data from the audio buffer to an audio interface, wherein the first DMA unit generates a first interrupt signal when the audio buffer is emptied, anda control logic that determines when the first unit exits a low power mode.
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Abstract
An audio processing system includes a first unit including a central processing unit (CPU) and a top domain. A system memory unit stores decoded audio data and a power management unit is configured to control power supply to the first unit and the system memory unit. An audio sub-system generates a first interrupt signal when an audio buffer, which temporarily stores the audio data, is emptied and determines whether the first unit should exit a low power mode in response to the first interrupt signal.
21 Citations
20 Claims
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1. An audio processing system comprising:
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a storage domain including a system memory unit; a first unit including a central processing unit (CPU) and a top domain, wherein the CPU decodes audio data stored in the storage domain to generate decoded audio data that is stored in the system memory unit; a power management unit configured to provide at least one power supply signal to the first unit and the system memory unit; and an audio sub-system including; an audio buffer that stores decoded audio data received from the system memory unit, a first Direct Memory Access (DMA) unit that moves decoded audio data from the audio buffer to an audio interface, wherein the first DMA unit generates a first interrupt signal when the audio buffer is emptied, and a control logic that determines when the first unit exits a low power mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An audio processing system configured to operate in a playback mode, the audio processing system comprising:
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a storage domain including a system memory unit that stores audio data, and is selectively configured to operate in a low power mode and a normal power mode; a first unit including a central processing unit (CPU) and a top domain, wherein the CPU decode the audio data to generate decoded audio data, and the CPU is selectively configured to operate in the low power mode and the normal power mode; an alive domain including a power management unit that provides at least one power supply signal to the first unit and the system memory unit in response to a user input signal indicating operation of the audio processing system in the playback mode; and an audio sub-system including; an audio buffer that stores decoded audio data, a first Direct Memory Access (DMA) unit that moves decoded audio data from the audio buffer to an audio interface, wherein the first DMA unit generates a first interrupt signal when the audio buffer is emptied, and a control logic that determines when the CPU operates in the low power mode. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method of operating an audio processing system, comprising:
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emptying decoded audio data from an audio buffer to an audio interface; generating a first interrupt signal and a power ON signal in response to the emptying of the audio buffer; activating a system memory unit storing decoded audio data in response to the power ON signal; incrementing a count value in response to the first interrupt signal; generating a wake-up signal when the count value reaches a count value threshold; activating a Central Processing Unit (CPU) to decode audio data to generate decoded audio data; and storing the decoded audio data in a stream buffer. - View Dependent Claims (17, 18, 19, 20)
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Specification