METHOD FOR FORMING DEEP TRENCH ISOLATION FOR RF DEVICES ON SOI
First Claim
1. A semiconductor device comprising:
- a silicon-on-insulator (SOI) substrate having a first region and a second region, the SOI substrate including a vertical stack of a first semiconductor substrate, a buried insulating layer, and a second semiconductor substrate arranged from bottom to top in the first region, respectively;
a plurality of transistors on the second semiconductor substrate;
a deep trench isolation exposing a surface of the first semiconductor substrate in the second region; and
a dielectric capping layer over a bottom and sidewalls of the deep trench isolation and the second semiconductor substrate.
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Abstract
A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a SOI substrate having shallow trench isolations (STIs) and transistors formed within and on the second semiconductor substrate, respectively. The method also includes forming a hard mask over the first region and removing the STIs, the transistors, the second semiconductor substrate and the buried insulating layer in the second region using the hard mask as a mask, and forming a capping layer covering the deep trench isolation and the second semiconductor substrate including the transistors.
6 Citations
5 Claims
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1. A semiconductor device comprising:
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a silicon-on-insulator (SOI) substrate having a first region and a second region, the SOI substrate including a vertical stack of a first semiconductor substrate, a buried insulating layer, and a second semiconductor substrate arranged from bottom to top in the first region, respectively; a plurality of transistors on the second semiconductor substrate; a deep trench isolation exposing a surface of the first semiconductor substrate in the second region; and a dielectric capping layer over a bottom and sidewalls of the deep trench isolation and the second semiconductor substrate. - View Dependent Claims (2, 3, 4, 5)
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Specification