SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

• US 20160276462A1
• Filed: 05/26/2016
• Published: 09/22/2016
• Est. Priority Date: 02/26/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHIANG, Tsung-Yu, CHEN, Kuang-Hsin
• Granted Patent: US 9,704,970 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence

Abstract

A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer. The contact plug has no contact-to-gate short issue to the gate structure.

Claims

1. A method of fabricating semiconductor device comprising:

forming a dummy gate structure with a dummy gate electrode and source/drain regions adjacent to the dummy gate structure over a substrate;

depositing an etch stop layer over the source/drain regions;

depositing a protective layer over the etch stop layer;

depositing an interlayer dielectric layer over the etch stop layer;

annealing the interlayer dielectric layer;

forming a metal gate structure by replacing part of the dummy gate structure;

depositing an isolation layer over the metal gate structure;

forming a contact opening through the interlayer dielectric layer to expose the source/drain regions; and

forming a contact plug in the contact opening and on the metal gate structure.

2. The method of claim 1, wherein forming the metal gate structure by replacing part of the dummy gate structure comprises:

removing the dummy gate electrode;

depositing a gate dielectric layer in the gate structure;

depositing a work function layer over the gate dielectric layer; and

forming a metal electrode over the work function layer.

3. The method of claim 1, wherein forming the contact opening through the interlayer dielectric layer to expose the source/drain regions comprises:

etching part of the interlayer dielectric layer and the protective layer; and

etching part of the etch stop layer to contact the source/drain regions.

4. The method of claim 1, wherein in depositing the protective layer over the etch stop layer, a thickness of the protective layer is in a range from about 1 nm to about 5 nm.

5. The method of claim 1, wherein in depositing the interlayer dielectric layer over the etch stop layer, a material of the interlayer dielectric layer includes flowable oxide.

6. The method of claim 1, wherein in depositing an etch stop layer over the source/drain regions, the etch stop layer overlies the dummy gate structure and the source/drain regions.

7. The method of claim 6, further comprising polishing the etching stop layer to expose the dummy gate structure after annealing the interlayer dielectric layer.

8. The method of claim 6, wherein in depositing the protective layer over the etch stop layer, the protective layer conformally overlies the etch stop layer.

9. The method of claim 6, wherein in depositing the protective layer over the etch stop layer, the protective layer overlies the etch stop layer without covering the dummy gate structure.

10. A method of fabricating semiconductor device comprising:

forming a dummy gate structure with a dummy gate electrode and source/drain. ns adjacent to the dummy gate structure over a substrate;

depositing an etch stop layer over the dummy gate structure and the source/drain regions;

depositing a protective layer over the etch stop layer overlying the source/drain regions;

depositing an interlayer dielectric layer over the protective layer;

annealing the interlayer dielectric layer;

polishing the etch stop layer to expose the dummy gate structure;

forming a metal gate electrode by replacing part of the dummy gate structure;

depositing an isolation layer over the metal gate electrode;

forming a contact opening through the interlayer dielectric layer to expose the source/drain regions; and

forming a contact plug in the contact opening and on the isolation layer.

11. The method of claim 10, wherein in depositing a protective layer over the etch stop layer overlying the source/drain regions, the protective layer conformally overlies the etch stop layer.

12. The method of claim 10, wherein forming the metal gate structure by replacing part of the dummy gate structure comprises:

removing the dummy gate electrode;

depositing a gate dielectric layer in the gate structure;

depositing a work function layer over the gate dielectric layer; and

forming a metal electrode over the work function layer.

13. The method of claim 10, wherein forming the contact opening through the interlayer dielectric layer to expose the source/drain regions comprises:

etching part of the interlayer dielectric layer and the protective layer; and

etching part of the etch stop layer to contact the source/drain regions.

14. The method of claim 10, wherein in forming the dummy gate structure with the dummy gate electrode and the source/drain regions, the dummy gate structure further comprises a spacer next to the dummy gate electrode.

15. A semiconductor device, comprising:

a substrate;

a gate structure over the substrate comprising;

a gate dielectric layer over the substrate;

a gate electrode over the gate dielectric layer;

an isolation layer over the gate electrode; and

a spacer next to each of the two sides of the gate electrode;

source/drain regions adjacent to the pair of spacers in the substrate;

an etch stop layer next to the pair of spacers and overlying the substrate;

a contact plug extending into the source/drain region and partially overlapping the isolation layer;

a protective layer over the etch stop layer overlying the substrate; and

an interlayer dielectric layer over the protective layer.

16. The semiconductor device of claim 15, wherein the protective layer covers the etch stop layer next to the spacer without the contact plug.

17. The semiconductor device of claim 15, wherein a refractive index of a material of the interlayer dielectric layer is in a range from about 2.5 to about 4.

18. The semiconductor device of claim 15, wherein a refractive index of a material of the protective layer is in a range from about 1.4 to about 2.

19. The semiconductor device of claim 15, wherein a material of the protective layer is selected from the group consisting of SiON, SiOCN, and SiO₂.

20. The semiconductor device of claim 15, wherein a thickness of the etch stop layer is thinner than that of the isolation layer.