WAFER LEVEL CHIP SCALE PACKAGED MICRO-ELECTRO-MECHANICAL-SYSTEM (MEMS) DEVICE AND METHODS OF PRODUCING THEREOF

• US 20160297674A1
• Filed: 04/10/2015
• Published: 10/13/2016
• Est. Priority Date: 04/10/2015
• Status: Active Grant

• Current Assignee: Memsic Semiconductor (Wuxi) Co., Ltd. (MZ Investment Holdings Ltd.)
• Original Assignee: Memsic Incorporated (MZ Investment Holdings Ltd.)
• Inventors: Man, Piu Francis, Cheng, Anru Andrew
• Granted Patent: US 9,682,854 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81B 2207/095 through the lid
• CPC Class Codes: B81B 2207/097 Interconnects arranged on the substrate or the lid, and covered by the package seal
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: B81C 1/00293 maintaining a controlled atmosphere with processes not provided for in B81C1/00285
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/0145 Hermetically sealing an opening in the lid
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 2224/11 Manufacturing methods

Abstract

Packaged MEMS devices are described. One such device includes a substrate having an active surface with an integrated circuit. Two substrate pads are formed on the substrate; one pad is a closed ring pad. The device also includes a cap wafer with two wafer pads. One of these wafer pads is also a closed ring pad. A hermetic seal ring is formed by a first bonding between the two ring pads. The device has a gap between the substrate and the cap wafer. This gap may be filled with a pressurized gas. An electrical connection is formed by a second bonding between one substrate pad and one wafer pad. An electrical contact is disposed over the cap wafer. The device also includes an insulation layer between the electrical contact and the cap wafer. Methods of producing the packaged MEMS devices are also described.

Claims

1. A packaged micro-electro-mechanical-system (MEMS) device comprising:

a silicon substrate having a first general planar surface;

at least two substrate pads formed on said first general planar surface, wherein at least one substrate pad is a first closed ring pad;

at least one silicon cap wafer having a second general planar surface with at least two wafer pads, wherein at least one wafer pad is a second closed ring pad, said at least one silicon cap wafer also having a third slanted surface with an angle to said second general planar surface, said at least one silicon cap wafer also having a fourth general planar surface wherein said fourth general planar surface is opposite to the second general planar surface;

at least one hermetic seal ring formed between the first general planar surface and the second general planar surface by a first bonding between said first closed ring pad and said second closed ring pad;

at least one gap formed between said silicon substrate and said at least one silicon cap wafer, wherein said at least one gap is filled with a pressurized gaseous species;

at least one electrical connection formed by a second bonding between at least one of the at least two substrate pads and at least one of the at least two wafer pads;

at least one electrical contact formed over said at least one silicon cap wafer, wherein a first portion of said at least one electrical contact is formed over said fourth general planar surface, a second portion of said at least one electrical contact is formed over said third slanted surface, and a third portion of said at least one electrical contact is formed over said at least one electrical connection; and

an insulation layer formed between said at least one electrical contact and said at least one silicon cap wafer.

2. The packaged MEMS device according to claim 1, wherein the said silicon substrate comprises an active surface with an integrated circuit formed on said first general planar surface.

3. The packaged MEMS device according to claim 1, wherein the at least one silicon cap wafer comprises an active surface with an integrated circuit formed on said second general planar surface.

4. The packaged MEMS device according to claim 1, wherein the at least two substrate pads comprise at least one of:

aluminum, copper, gold, silicon, titanium, tin, indium, and germanium.

5. The packaged MEMS device according to claim 1, wherein the at least two wafer pads comprise at least one of:

aluminum, copper, gold, silicon, titanium, tin, indium, and germanium.

6. The packaged MEMS device according to claim 1, wherein a pressure of the pressurized gaseous species ranges from one of:

1 bar to 10 bar;

1 bar to 5 bar; and

1 bar to 3 bar.

7. The packaged MEMS device according to claim 1, wherein the pressurized gaseous species comprises at least one of:

sulphur hexafluoride, carbon dioxide, xenon, and 2,3,3,3-Tetrafluoropropene (HFO1234yf), or propane.

8. The packaged MEMS device according to claim 1, wherein the insulation layer comprises at least one of:

epoxy, silicon nitride, silicon oxide, silicon oxynitride, a solder mask, polyimide, benzocyclobutene (BCB), parylene, polynaphthalenes, fluorocarbons and acrylates.

9. The packaged MEMS device according to claim 1, further comprising at least one recess in the silicon substrate, wherein the at least one recess defines at least one additional gap.

10. The packaged MEMS device according to claim 1, further comprising at least one recess in the silicon cap wafer, wherein the at least one recess defines at least one additional gap.

11. The packaged MEMS device according to claim 1, wherein at least one of:

the first bonding and the second bonding comprise a eutectic bonding, and the eutectic bonding comprises at least one of;

gold-tin, copper-tin, gold-silicon, gold-indium, gold-germanium, and aluminum-germanium.

12. The packaged MEMS device according to claim 1, wherein at least one of:

the first bonding and the second bonding comprise a metal diffusion bonding, and the metal diffusion bonding comprises at least one of;

copper-copper, gold-gold, and silicon-titanium.

13. The packaged MEMS device according to claim 1, wherein the at least one gap formed between said silicon substrate and said at least one silicon cap wafer is further formed between said silicon substrate, the third slanted surface and said at least one silicon cap wafer,

said third slanted surface is internal to the packaged MEMS device, and

the at least one electrical contact formed over said at least one silicon cap wafer is entirely formed over said at least one silicon cap wafer.

14. The packaged MEMS device according to claim 1, further comprising at least one through silicon via (TSV) formed through the at least one wafer pad, wherein said at least one TSV is at least partly filled with a conductive material, wherein a fourth portion of said at least one electrical contact is formed through the at least one TSV.

15. A method of producing a packaged micro-electro-mechanical-system (MEMS) device comprising the steps of:

providing a silicon substrate having a first general planar surface;

forming at least two substrate pads on said first general planar surface, wherein at least one substrate pad is a first closed ring pad;

providing at least one silicon cap wafer having a second general planar surface with at least two wafer pads, wherein at least one wafer pad is a second closed ring pad, said at least one silicon cap wafer also having a third slanted surface with an angle to said second general planar surface, said at least one silicon cap wafer also having a fourth general planar surface;

forming at least one hermetic seal ring between the first general planar surface and the second general planar surface by a first bonding between said first closed ring pad and said second closed ring pad;

forming at least one gap between said silicon substrate and said at least one silicon cap wafer, wherein said at least one gap is filled with a pressurized gaseous species;

forming at least one electrical connection by a second bonding between at least one of the at least two substrate pads and at least one of the at least two wafer pads;

forming at least one electrical contact on said at least one silicon cap wafer, wherein a first portion of said at least one electrical contact is formed over said fourth general planar surface, a second portion of said at least one electrical contact is formed over said third slanted surface, and a third portion of said at least one electrical contact is formed over said at least one electrical connection; and

forming an insulation layer between said at least one electrical contact and said at least one silicon cap wafer.

16. The method according to claim 15, further comprising forming an active surface with an integrated circuit on said first general planar surface.

17. The method according to claim 15, further comprising forming an active surface with an integrated circuit on said second general planar surface.

18. The method according of claim 15, wherein at least one of:

the first bonding and the second bonding comprise one of;

a eutectic bonding and a metal diffusion bonding.

19. The method according of claim 15, wherein forming the at least one gap between said silicon substrate and said at least one silicon cap wafer comprises forming the at least one gap between said silicon substrate, said third slanted surface and said at least one silicon cap wafer,

wherein said third slanted surface is internal to the packaged MEMS device.

20. A method of producing a packaged micro-electro-mechanical-system (MEMS) device comprising the steps of:

providing a silicon substrate having a first general planar surface;

forming an active surface with an integrated circuit on said first general planar surface;

forming at least two substrate pads on said first general planar surface, wherein at least one substrate pad is a first closed ring pad;

providing a silicon cap wafer having a second general planar surface with at least two wafer pads, wherein at least one wafer pad is a second closed ring pad, said silicon cap wafer also having a third slanted surface with an angle to said second general planar surface, said silicon cap wafer also having a fourth general planar surface, wherein said fourth general planar surface is opposite to the second general planar surface;

forming at least one hermetic seal ring between the first general planar surface and the second general planar surface by a first bonding between said first closed ring pad and said second closed ring pad;

forming at least one gap between said silicon substrate and said at least silicon cap wafer;

forming at least one electrical connection by a second bonding between at least one of the at least two substrate pads and at least one of the at least two wafer pads;

forming at least one through silicon via (TSV) through the silicon cap wafer, wherein said at least one TSV is partly filled with a conductive material;

forming at least one electrical contact partly over and partly through said silicon cap wafer, wherein a first portion of said at least one electrical contact is formed over said fourth general planar surface, a second portion of said at least one electrical contact is formed over said third slanted surface, a third portion of said at least one electrical contact is formed through the at least one TSV, and a fourth portion of said at least one electrical contact is formed over said at least one electrical connection; and

forming an insulation layer between said at least one electrical contact and said silicon cap wafer.

21. The method according to claim 20, wherein at least one of:

the first bonding and the second bonding comprise one of;

a eutectic bonding and a metal diffusion bonding.

22. A packaged micro-electro-mechanical-system (MEMS) device comprising:

a silicon substrate having a first general planar surface;

an active surface with an integrated circuit formed on said first general planar surface;

at least two substrate pads formed on said first general planar surface, wherein at least one substrate pad is a first closed ring pad;

a silicon cap wafer having a second general planar surface with at least two wafer pads, wherein at least one wafer pad is a second closed ring pad, said silicon cap wafer also having a third general planar surface, wherein said third general planar surface is opposite to the second general planar surface;

at least one hermetic seal ring formed between the first general planar surface and the second general planar surface by a first bonding between said first closed ring pad and said second closed ring pad;

at least one cavity in the silicon substrate;

at least one other cavity in the silicon cap wafer;

at least one gap between said silicon substrate and said silicon cap wafer filled with a pressurized gaseous species and a pressure of the gaseous species ranges from one of;

1 bar to 10 bar;

1 bar to 5 bar; and

1 bar to 3 bar;

at least one electrical connection formed by a second bonding between at least one of the at least two substrate pads and at least one of the at least two wafer pads;

at least one through silicon via (TSV) formed through the silicon cap wafer, wherein said at least one TSV is at least partly filled with a conductive material;

at least one electrical contact partly formed over and partly formed through said silicon cap wafer, wherein a first portion of said at least one electrical contact is formed over said third general planar surface, a second portion of said at least one electrical contact is formed through the at least one TSV, and a third portion of said at least one electrical contact is formed over said at least one electrical connection; and

an insulation layer formed between said at least one electrical contact and said silicon cap wafer.

23. The packaged MEMS device according to claim 22, wherein at least one of:

the first bonding and the second bonding comprise one of;

a eutectic bonding and a metal diffusion bonding.

24. The packaged MEMS device according to claim 22, wherein the conductive material that at least partly fills said at least one TSV comprises at least one of:

in-situ doped polysilicon and copper.

25. A method of producing a packaged micro-electro-mechanical-system (MEMS) device comprising the steps of:

providing a silicon substrate having a first general planar surface;

forming an active surface with an integrated circuit on said first general planar surface;

forming at least two substrate pads on said first general planar surface, wherein at least one substrate pad is a first closed ring pad;

providing a silicon cap wafer having a second general planar surface with at least two wafer pads, wherein at least one wafer pad is a second closed ring pad, said silicon cap wafer also having a third general planar surface, wherein said third general planar surface is opposite to the second general planar surface;

forming at least one hermetic seal ring between the first general planar surface and the second general planar surface by a first bonding between said first closed ring pad and said second closed ring pad;

forming at least one cavity in the silicon substrate;

forming at least one other cavity in the silicon cap wafer;

forming at least one gap between said silicon substrate and said silicon cap wafer filled with a pressurized gaseous species and a pressure of the gaseous species ranges from one of;

1 bar to 10 bar;

1 bar to 5 bar; and

1 bar to 3 bar;

forming at least one electrical connection by a second bonding between at least one of the at least two substrate pads and at least one of the at least two wafer pads;

forming at least one through silicon via (TSV) through the silicon cap wafer, wherein said at least one TSV is at least partly filled with a conductive material;

forming at least one electrical contact partly over and partly through said silicon cap wafer, wherein a first portion of said at least one electrical contact is formed over said third general planar surface, a second portion of said at least one electrical contact is formed through the at least one TSV, and a third portion of said at least one electrical contact is formed over said at least one electrical connection; and

forming an insulation layer between said at least one electrical contact and said silicon cap wafer.

26. The method according to claim 25, wherein at least one of:

the first bonding and the second bonding comprises one of;

a eutectic bonding and a metal diffusion bonding.

27. A packaged micro-electro-mechanical-system (MEMS) device comprising:

a silicon substrate having a first general planar surface, and a second general planar surface, wherein the second general planar surface is on a side opposite the first general planar surface;

an active surface with an integrated circuit formed on said first general planar surface;

at least one substrate pad formed on said first general planar surface;

at least one bonding layer;

at least one chip scale packaging layer;

at least one bonding formed between the at least one chip scale packaging layer and the silicon substrate;

at least one recess in the silicon substrate;

at least one other recess in the at least one chip scale packaging layer;

at least one gap formed between said silicon substrate and a cap wafer, wherein the at least one chip scale packaging layer is filled with a pressurized gaseous species and a pressure of the gaseous species ranges from one of;

1 bar to 10 bar;

1 bar to 5 bar; and

1 bar to 3 bar;

at least one through silicon via (TSV) formed through the silicon substrate connected to at least one substrate pad, wherein said at least one TSV is at least partly filled with a conductive material;

at least one electrical contact partly formed over and partly formed through said silicon substrate, wherein a first portion of said at least one electrical contact is formed over said second general planar surface, a second portion of said at least one electrical contact is formed through the at least one TSV; and

an insulation layer formed between said at least one electrical contact and said silicon substrate.

28. The packaged MEMS device according to claim 27, wherein the conductive material that at least partly fills said at least one TSV comprises at least one of:

in-situ doped polysilicon and copper.

29. The packaged MEMS device according to claim 27, wherein the at least one substrate pad is a first-level metal layer of a standard complementary metal-oxide-semiconductor (CMOS) process.

30. The packaged MEMS device according to claim 27, wherein the at least one bonding comprises one of:

a eutectic bonding and a metal diffusion bonding.

31. The packaged MEMS device according to claim 27, wherein the at least one bonding is an adhesion layer bonding.

32. The packaged MEMS device according to claim 31, wherein the adhesion layer bonding comprises an epoxy.

33. A packaged MEMS device according to claim 27, further comprising a recess in the silicon substrate defining an additional gap.

34. A packaged MEMS device according to claim 27, further comprising a recess in the at least one chip scale packaging layer defining an additional gap.

35. The packaged MEMS device according to claim 27, wherein the conductive material that at least partly fills said at least one TSV comprises at least one of:

in-situ doped polysilicon and copper.

36. The packaged MEMS device according to claim 27, wherein the at least one gap is filled with a pressurized gaseous species and a pressure of the gaseous species ranges from one of:

1 bar to 10 bar; and

1 bar to 3 bar.

37. A method of producing a packaged micro-electro-mechanical-system (MEMS) device comprising the steps of:

providing a silicon substrate having a first general planar surface, and a second general planar surface, wherein at least a second general planar surface is on a side opposite the first general planar surface;

forming an active surface with an integrated circuit on said first general planar surface;

forming at least one substrate pad on said first general planar surface;

forming at least one bonding layer;

providing at least one chip scale packaging layer;

forming at least one bonding between the at least one chip scale packaging layer and the silicon substrate;

forming at least one recess in the silicon substrate;

forming at least one other recess in the at least one chip scale packaging layer;

forming at least one gap between said silicon substrate and a cap wafer, wherein the at least one chip scale packaging layer filling with pressurized gaseous species at a pressure of one of;

1 bar to 10 bar;

1 bar to 5 bar; and

1 bar to 3 bar;

forming at least one through silicon via (TSV) through the silicon substrate connected to at least one substrate pad, wherein said at least one TSV is at least partly filled with a conductive material;

forming at least one electrical contact partly over and partly through said silicon substrate, wherein a first portion of said at least one electrical contact is formed over said second general planar surface, and a second portion of said at least one electrical contact is formed through the at least one TSV; and

forming an insulation layer between said at least one electrical contact and said silicon substrate.

38. The method according to claim 37, wherein forming the at least one substrate pad comprises forming a first-level metal layer of a standard complementary metal-oxide-semiconductor (CMOS) process.

39. The method according to claim 37, wherein the at least one bonding comprises one of:

a eutectic bonding and a metal diffusion bonding.

40. The method according to claim 37, wherein the at least one bonding comprises an epoxy adhesion bonding.

41. A fabrication process for a packaged integrated micro-electro-mechanical-system (MEMS) device which includes at least:

procuring a silicon cap wafer having a first general planar surface and a second general planar surface, wherein said second general planar surface is opposite to the first general planar surface;

following completion of the procuring of the silicon cap wafer, forming trenches on the first general planar surface by selectively etching the silicon cap wafer using either dry or wet silicon etching,

following completion of the forming of the trenches, depositing a liner passivation layer along sidewalls of the trenches and on the first general planar surface,

following completion of the deposition of the liner passivation layer, forming through silicon vias (TSVs) by depositing a first conductive material along the sidewalls of the trenches and on the first general planar surface,

following completion of the formation of the TSVs, performing chemical mechanical polishing on the first general planar surface to provide a planar surface,

following completion of the chemical mechanical polishing of the first general planar surface, forming wafer pads on said first general planar surface by deposition of a second conductive material and selectively etching the second conductive material,

following completion of the formation of the wafer pads, forming a first cavity by selectively etching said first general planar surface using either dry or wet etching,

forming an active surface with an integrated circuit on a third general planar surface on a silicon substrate having substrate pads,

following completion of the formation of the active surface, forming a second cavity on the third general planar surface of the silicon substrate by selectively etching of the silicon substrate,

following completion of the formation of the second cavity, performing hermetic bonding between the wafer pads on the first general planar surface and the substrate pads on the third general planar surface by forming eutectic or metal diffusion bonding at an elevated temperature, wherein the first cavity and the second cavity are filled with a pressurized gaseous species, a pressure of the gaseous species ranges from one of;

1 bar to 10 bar;

1 bar to 5 bar; and

1 bar to 3 bar, and the gaseous species comprises at least one of;

sulphur hexafluoride, carbon dioxide, xenon, and 2,3,3,3-Tetrafluoropropene (HFO1234yf), or propane,

following completion of the hermetic bonding, performing chemical mechanical polishing on the second general planar surface to expose individual TSVs,

following completion of the chemical mechanical polishing of the second general planar surface, revealing vias by depositing a passivation layer and selectively etching said passivation layer,

following completion of the revealing of the vias, forming a redistribution layer by depositing a metal layer and etching said metal layer, and

following completion of the formation of the redistribution layer, forming a top passivation layer and selectively etching said top passivation layer to expose the redistribution layer.

42. The fabrication process according to claim 41, wherein the first conductive material is one of:

in-situ polysilicon or copper.

43. The fabrication process according to claim 41, wherein the wafer pads and the substrate pads comprise at least one of:

aluminum, copper, gold, silicon, titanium, tin, indium, and germanium.

44. The fabrication process according to claim 41, further comprising depositing a filling material following completion of the formation of the TSVs,

wherein the chemical mechanical polishing is further performed following completion of the deposition of the filling material.

45. A fabrication process for a packaged integrated micro-electro-mechanical-system (MEMS) device which includes at least:

forming an active surface with an integrated circuit having a complementary metal-oxide-semiconductor (CMOS) metal layer as substrate pads on a first general planar surface on a silicon substrate and having a passivation layer on a second general planar surface which is opposite to the first general planar surface,

following completion of the formation of the active surface, forming through silicon via (TSV) trenches by selectively etching from the second general planar surface using either dry or wet silicon etching,

following completion of the formation of the TSV trenches, depositing a passivation layer along sidewalls of the TSV trenches and on the second general planar surface,

following completion of the deposition of the passivation layer, revealing vias by blank etching of the passivation layer to expose the vias at bottoms of the TSV trenches,

following completion of the revealing of the vias, forming a redistribution layer by depositing conductive material along the sidewalls of the TSV trenches and on the second general planar surface and selectively etching away the conductive material on the second general planar surface of the silicon substrate,

following completion of the formation of the redistribution layer, forming a cavity opening by selectively etching the passivation layer on the first general planar surface,

following completion of the formation of the cavity opening, forming a first cavity by dry etching said silicon substrate,

forming a second cavity on a chip scale packaging layer by selectively etching on a third general planar surface of said chip scale packaging layer,

following completion of the formation of the second cavity, performing bonding between said chip scale packaging layer and said CMOS metal layer by forming one of;

epoxy adhesion bonding, eutectic diffusion bonding or metal diffusion bonding at an elevated temperature filling with a pressurized gaseous species, wherein a pressure of the gaseous species ranges from one of;

1 bar to 10 bar;

1 bar to 5 bar; and

1 bar to 3 bar, and the gaseous species comprises at least one of;

sulphur hexafluoride, carbon dioxide, xenon, and 2,3,3,3-Tetrafluoropropene (HFO1234yf), or propane, and

following completion of the bonding, forming a passivation layer covering the redistribution layer on the second general planar surface of the CMOS metal layer and selectively etching said passivation layer to form via openings.

46. The fabrication process according to claim 45, wherein the conductive material is copper.

47. A fabrication process for a packaged integrated micro-electro-mechanical-system (MEMS) device which includes at least:

forming, on a complementary metal-oxide-semiconductor (CMOS) wafer, an active surface with an integrated circuit prior to formation of a metal layer in a CMOS process, having a passivation layer on a first general planar surface of a silicon substrate and having a second general planar surface opposite to the first general planar surface,

following completion of the formation of the active surface, forming through silicon via (TSV) trenches by selectively etching from first general planar surface using either dry or wet silicon etching,

following completion of the formation of the TSV trenches, depositing a passivation layer along sidewalls of the TSV trenches and on the first general planar surface,

following completion of the deposition of the passivation layer, performing TSV formation by depositing conductive material along the sidewalls of the TSV trenches and on the second general planar surface,

following completion of the TSV formation, performing chemical mechanical polishing of the first general planar surface,

following completion of the chemical mechanical polishing of the first general planar surface, completing remaining CMOS processes including deposition of metal layers, passivation layers, and via openings,

following completion of the remaining CMOS processes, forming a first cavity on the first general planar surface by selectively dry etching said silicon substrate,

forming a second cavity on a chip scale packaging layer by selectively etching on a third general planar surface of said chip scale packaging layer,

following completion of the formation of the second cavity on the chip scale packaging layer, performing bonding between said chip scale packaging layer and said silicon CMOS wafer by forming one of;

epoxy adhesion bonding, eutectic diffusion bonding, or metal diffusion bonding at an elevated temperature, wherein the first cavity and the second cavity are filled with a pressurized gaseous species, a pressure of the gaseous species ranges from one of;

1 bar to 10 bar;

1 bar to 5 bar; and

1 bar to 3 bar, and the gaseous species comprises at least one of;

sulphur hexafluoride, carbon dioxide, xenon, and 2,3,3,3-Tetrafluoropropene (HFO1234yf), or propane,

following completion of the bonding, performing chemical mechanical polishing of the second general planar surface,

following completion of the chemical mechanical polishing of the second general planar surface, forming a first passivation layer covering over the second general planar surface and selectively etching said passivation layer to form via openings,

following completion of the formation of the first passivation layer, forming a redistribution layer by depositing a conductive material on second general planar surface and selectively etching away said conductive material; and

following completion of the formation of the redistribution layer, forming a second passivation layer which covers over the redistribution layer and selectively etching said second passivation layer to form additional via openings.

48. The fabrication process according to claim 47, wherein the conductive material is copper.