THIN FILM TRANSISTOR PANEL HAVING AN ETCH STOPPER ON SEMICONDUCTOR

• US 20170077246A1
• Filed: 11/04/2016
• Published: 03/16/2017
• Est. Priority Date: 02/11/2010
• Status: Abandoned Application

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: YUN, Pil-Sang, KIM, Ki-Won, RYU, Hye-Young, LEE, Woo-Geun, CHOI, Seung-Ha, YOUN, Jae-Hyoung, CHUNG, Kyoung-Jae, LEE, Young-Wook, LEE, Je-Hun, YOON, Kap-Soo, KIM, Do-Hyun, YANG, Dong-Ju, CHOI, Young-Joo
• Application Number:
  US15/343,234
• Publication Number:
  US 20170077246A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/465 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/469
• CPC Class Codes: H01L 21/475 using masks
• CPC Class Codes: H01L 21/47573 Etching the layer
• CPC Class Codes: H01L 21/47635 After-treatment of these layers
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Claims

1. A method for forming a panel comprising a thin film transistor, the method comprising:

forming an oxide semiconductor pattern comprising a channel region;

forming an etch stopper at a position corresponding to the channel region; and

forming a first electrode and a second electrode spaced apart from the first electrode, the channel region configured to connect the first electrode to the second electrode,

wherein the etch stopper and the oxide semiconductor pattern are formed using a first mask.

2. The method of claim 1, further comprising:

disposing a first conductive layer on a substrate;

disposing a first insulating layer on the first conductive layer;

disposing an oxide semiconductor layer on the first insulating layer; and

disposing an etch stop layer on the oxide semiconductor layer;

wherein the etch stopper and the oxide semiconductor pattern are formed by patterning the etch stop layer and the oxide semiconductor layer using the first mask.

3. The method of claim 2, wherein patterning the etch stop layer and the oxide semiconductor layer comprises forming a photoresist pattern using the first mask.

4. The method of claim 3, wherein patterning the etch stop layer and the oxide semiconductor layer further comprises etching the etch stop layer having the photoresist pattern thereon to form an interim etch stopper.

5. The method of claim 4, wherein patterning the etch stop layer and the oxide semiconductor layer further comprises etching the oxide semiconductor layer having the interim etch stopper thereon to form the oxide semiconductor pattern.

6. The method of claim 5, wherein patterning the etch stop layer and the oxide semiconductor layer further comprises etching the interim etch stopper to form the etch stopper.

7. The method of claim 6, wherein the interim etch stopper is formed by dry etching the etch stop layer.

8. The method of claim 7, wherein the oxide semiconductor pattern is formed by wet etching the oxide semiconductor layer.

9. The method of claim 8, wherein the etch stopper is formed by dry etching the interim etch stopper.

10. The method of claim 9, wherein etching the interim etch stopper to form the etch stopper further comprises etching the first insulating layer.

11. The method of claim 6, further comprising:

forming a second conductive layer on the etch stopper and the oxide semiconductor pattern,

wherein the second conductive layer is patterned to form the first electrode and the second electrode.

12. The method of claim 11, further comprising:

forming a second insulating layer on the first electrode and the second electrode;

patterning the second insulating layer to form a contact hole exposing the first electrode; and

forming a third conductive layer on the second insulating layer;

patterning the third conductive layer to form a third electrode,

wherein the third electrode is connected to the first electrode via the contact hole.

13. The method of claim 12, wherein the second insulating layer comprises a passivation layer.

14. The method of claim 12, wherein the second insulating layer comprises a color filter.

15. The method of claim 12, further comprising:

patterning the first conductive layer to form a fourth electrode, the fourth electrode being disposed under the etch stopper and the oxide semiconductor pattern.

16. The method of claim 15, wherein the first conductive layer is patterned using a second mask, the second conductive layer is patterned using a third mask, the second insulating layer is patterned using a fourth mask, and the third conductive layer is patterned using a fifth mask.