METHOD FOR GENERATING HIGHLY EFFICIENT HARMONICS FREE DC TO AC INVERTERS

• US 20170201170A1
• Filed: 03/26/2017
• Published: 07/13/2017
• Est. Priority Date: 03/26/2017
• Status: Abandoned Application

• Current Assignee: Ahmed Fayez Abu-Hajar
• Original Assignee: Ahmed Fayez Abu-Hajar
• Inventors: ABU-HAJAR, AHMED FAYEZ
• Application Number:
  US15/469,540
• Publication Number:
  US 20170201170A1
• Time in Patent Office: Days
• CPC Class Codes: H02M 1/12 Arrangements for reducing harmonics from ac input or output
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 7/48 using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: H02M 7/49 Combination of the output voltage waveforms of a plurality of converters
• CPC Class Codes: H02M 7/497 sinusoidal output voltages being obtained by combination of several voltages being out of phase

Abstract

This invention presents a highly efficient harmonics free DC-AC power inverter using a pair of push-pull switches with feedback loop that acts as a voltage regulator. The feedback loop voltage regulator uses a series-shunt feedback amplifier to regulate the output voltage by amplifying the error signal between a pure sine wave referenced signal and the measured output voltage signal. A step-up low power transformer is used to step-up the triggering pulse at gates of the push-pull solid state switches to the desired rated output voltage so that the output voltage becomes harmonic free sine wave, but high voltage feedback amplifier, if feasible, maybe used without using the transformer. The reference signal may be synchronized with the grid for on grid applications, but it can also be used for stand alone loads. In order to optimally minimized the conduction power loss across the push-pull solid state switches of the DC-AC inverter, the positive voltage V+ and the negative voltage V− must be regulated and controlled, so that the voltage across the push-pull switches are minimized. Hence, two DC-DC converters are used to generate the regulated voltages V+ and V−. Each of those voltages is controlled using a feedback loop that drives the pwm of the DC-DC converter. At this point, the conduction power loss of the DC-AC push-pull solid state switches are optimally minimized, but the DC-DC converters are not. In order to minimize the conduction power loss of the DC-DC converters, two multilevel converters with n-array series voltage sources, or n-array series capacitors, are used. The voltage level at the top of each capacitor is carefully selected so that the overall conduction power loss of the DC-DC converters is minimized. The power conduction power loss proportional to the number of levels used but this comes at higher cost and complexity.

Claims

1. A highly efficient harmonics free DC to AC inverter system that includes unregulated DC voltage source, that may be supplied by a battery or photovoltaic cells or any unregulated voltage source, followed by multilevel voltage controlled DC-DC converters that produce positive half wave regulated sinusoidal voltage V₊ and negative half wave regulated sinusoidal voltage V, followed by a DC-AC inverter that is driven by harmonics suppressor voltage regulator in a feedback loop, in which the DC-AC inverter supplies the load with harmonics free sinusoidal voltage at rated values, and in which the overall system contains a controller that controls the multilevel DC-DC converters and the rated voltage based on the load current and power factor.

2. The DC-AC inverter of claim 1 uses a pair of push-pull solid state switches, such as NOMOS and PMOS switches, that are driven by precise triggering pulses in order to generate harmonics free voltage at the load.

3. The DC-DC converters of claim 1 generates two regulated voltages, V+ and V−

, in such a way that minimizes the voltages across the pair of the push-pull solid state switches of DC-AC inverter of claim 1 by making V+ to follow the output voltage on the positive half cycle of the current, and by making V−

to follow the output voltage on the negative half cycle of the current.

4. The feedback loop of voltage regulator of claim 1 wherein uses a harmonics free sine wave as a reference signal to regulate the voltage at the load by sending precise triggering pulses in the feedback loop to drive the push-pull solid state switches of the DC-AC inverters.

5. The control unit of claim 1 wherein uses a computation machine, such as microcontroller or microprocessor and/or analog systems with or without feedback topologies, to the control the entire system by sending control signals to drive the switches of the DC-DC converters, the voltage regulator and the DC-AC inverter.

6. The combined coupling of the voltage regulator and the push-pull solid state switches of the DC-AC inverter of claim 1 wherein are used in a feedback configuration to provide harmonics free sine wave voltage at the output.

7. The feedback loop voltage regulator of claim 1 wherein uses a low power step-up transformer or a sequence of cascaded transformers or high voltage electronics or any other electronics device to step up the triggering pulses of the push-pull solid state switches so that it generates harmonics free voltage at the output.

8. A method for generating a highly efficient DC-AC inverter with minimum power conduction loss across the push-pull solid state switches of the DC-AC inverter is obtained by applying the maximum allowable triggering signals at the gates of the switches while minimizing the voltage across the push-pull solid state switches of the DC-AC inverter by using two DC-DC converters, such as Buck DC-DC converters or any other DC-DC converter, where one converter generates a regulated positive half cycle voltage V+ by using a non-linear pwm via feedback loop, or other mechanism, that generates precise pwm pulses to the driver circuit of the positive voltage converter, and the other converter generates a regulated negative half cycle voltage V−

by using non-linear pwm via feedback loop, or other mechanism, that generates the pwm pulses to the negative converter switch driver.

9. The inductors and capacitors of the converters, such as Buck or Boost or Buck-Boost or Cuk or other types of converters, of claim 8 wherein are selected to make the converters operate in the continuous mode for a large range around the nominal rated current.

10. The regulated voltages V+ of claim 8 wherein uses a high gain and high bandwidth amplifier in the feedback which measures the regulated voltage V+ and compares it with a referenced half wave sinusoidal signal so that the regulated voltage V+ follows the voltage across the DC-AC inverter switch such that the conduction power loss of the DC-AC inverter is minimized during positive half cycle of the of the current.

11. The regulated voltages V−

of claim 8 wherein uses a high gain and high bandwidth amplifier in the feedback which measures the regulated voltage V1 and compares it with a referenced half wave sinusoidal signal so that the regulated voltage V−

follows the voltage across the DC-AC inverter switch such that the conduction power loss of the DC-AC inverter is minimized during negative half cycle of the of the current.

12. This invention includes two highly efficient multilevel DC-DC converters, where one converter is used to generate a regulated positive voltage V+ during the positive half cycle and the other converter is used to generate a regulated the negative voltage V−

during the negative half cycle, where each multilevel converter has an array of series connected capacitors, that act as voltage sources in series, and each capacitor is connected to its associated switch in series with a diode, where the diodes are used to prevents the flow of reversed currents, also each switch has its own driver circuit that is driven by a feedback amplifier in a feedback loop, where one feedback loop is used to regulate the positive voltage V+ of the converter and the other feedback loop is used to regulate the negative voltage V−

of the converter, and both converters have control signals that determine the conduction time interval for each switch.

13. The positive voltage multilevel DC-DC converter of claim 12 wherein generates a regulated positive half wave sinusoidal voltage that optimally minimizes the voltage across the push-pull switches of the DC-AC inverter during the current'"'"'s positive half cycle.

14. The negative voltage multilevel DC-DC converter of claim 12 wherein generates a negative half wave sinusoidal voltage that optimally minimizes the voltage across the push-pull switches of the DC-AC inverter during the current'"'"'s negative half cycle.

15. Each of the capacitors of claim 12 wherein is carefully selected based on the number of levels selected, so that the conduction power loss across the multilevel DC-DC converter is minimized.

16. Each switch of claim 12 wherein is conducting during a specific time interval that is determined such that the overall power loss across the DC-DC converter is minimized.

17. The duty cycle of the pwm signal for each switch of the multilevel DC-DC converters of claim 12 wherein is controlled during its conducting time interval using a high speed amplifier in the feedback loop, or other mechanism such as precise algorithm.

18. The feedback loop for each of the multilevel converters of claim 12 wherein uses a half wave rectified signal that is generated by the controller and compares it to the actual measured voltage to derive the pwm duty cycle of each switch during the switch conduction time interval.

19. The voltage step size and the conduction time intervals for each switch of claim 12 wherein are determined by finding the global minima of the conduction power losses across the converters using exhaustive search iterative numerical methods.

20. Each switch of the multilevel converter of claim 12 wherein has a series connected diode that prevents the current from flowing backward in the reverse direction as those switches are bidirectional.