STACKED NANOSHEET FIELD-EFFECT TRANSISTOR WITH AIRGAP SPACERS

• US 20180331232A1
• Filed: 05/09/2017
• Published: 11/15/2018
• Est. Priority Date: 05/09/2017
• Status: Active Application

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Frougier, Julien, Xie, Ruilong, Zang, Hui, Cheng, Kangguo, Yamashita, Tenko, Yeh, Chun-chen
• Granted Patent: US 10,269,983 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A fin is formed that includes a first nanosheet channel layer and a second nanosheet channel layer arranged in a vertical stack. A cavity is formed between a portion of the first nanosheet channel layer and a portion of the second nanosheet channel layer. An epitaxially-grown source/drain region is connected with the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer. A gate structure is formed that includes a section located in a space between the first nanosheet channel layer and the second nanosheet channel layer. The cavity is surrounded by the first nanosheet channel layer, the second nanosheet channel layer, the section of the gate structure, and the source/drain region to define an air gap spacer.

Claims

1. A structure for a field-effect transistor, the structure comprising:

a fin including a first nanosheet channel layer and a second nanosheet channel layer arranged in a vertical stack;

a gate structure including a section located vertically in a space between the first nanosheet channel layer and the second nanosheet channel layer;

a source/drain region connected with a portion of the first nanosheet channel layer and a portion of the second nanosheet channel layer; and

an air gap spacer surrounded by the portion of the first nanosheet channel layer, the portion of the second nanosheet channel layer, the section of the gate structure, and the source/drain region.

2. The structure of claim 1 further comprising:

a conformal dielectric layer includes a first portion arranged between the air gap spacer and the section of the gate structure.

3. The structure of claim 2 wherein the conformal dielectric layer includes a second portion arranged between the portion of the first nanosheet channel layer and the air gap spacer, and the conformal dielectric layer includes a third portion arranged between the portion of the second nanosheet channel layer and the air gap spacer.

4. The structure of claim 2 wherein the conformal dielectric layer is comprised of silicon nitride.

5. The structure of claim 2 wherein the fin is located on a substrate, the substrate includes a dielectric layer adjacent to the fin, the conformal dielectric layer has a portion located on the dielectric layer, and the fin and the portion of the conformal dielectric layer mask a first area on the dielectric layer.

6. The structure of claim 5 wherein the dielectric layer includes a second area adjacent to the first area, and the second area is thinner than the first area.

7. The structure of claim 6 wherein the source/drain region is arranged in vertical alignment with the second area.

8. The structure of claim 1 wherein the air gap spacer is arranged horizontally between the section of the gate structure and the source/drain region.

9. The structure of claim 8 wherein the air gap spacer is arranged vertically between the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer.

10. A method for forming a field-effect transistor, the method comprising:

forming a first fin that includes a first nanosheet channel layer and a second nanosheet channel layer arranged in a vertical stack;

forming a cavity between a portion of the first nanosheet channel layer and a portion of the second nanosheet channel layer;

epitaxially growing a source/drain region connected with the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer; and

forming a first gate structure including a section located in a space between the first nanosheet channel layer and the second nanosheet channel layer,

wherein the cavity is surrounded by the portion of the first nanosheet channel layer, the portion of the second nanosheet channel layer, the section of the first gate structure, and the source/drain region to define an air gap spacer.

11. The method of claim 10 wherein the first nanosheet channel layer includes a first vertical surface, the second nanosheet channel layer includes a second vertical surface, the first nanosheet channel layer is separated from the second nanosheet channel layer by a sacrificial semiconductor layer, and forming the cavity between the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer comprises:

laterally recessing the sacrificial semiconductor layer relative to the first vertical surface and the second vertical surface to form the cavity.

12. The method of claim 11 further comprising:

depositing a conformal dielectric layer inside the cavity; and

depositing a dielectric layer that fills the cavity to form a dielectric spacer and that covers the first vertical surface and the second vertical surface.

13. The method of claim 12 further comprising:

removing the dielectric layer from the first vertical surface and the second vertical surface with an isotropic etching process.

14. The method of claim 13 wherein the conformal dielectric layer is deposited on the first vertical surface and the second vertical surface, the dielectric layer is removed by the isotropic etching process from the first vertical surface and the second vertical surface without removing the dielectric spacer from the cavity, and further comprising:

before the source/drain region is epitaxially grown, removing the dielectric spacer from the cavity, the conformal dielectric layer from the first vertical surface, and the conformal dielectric layer from the second vertical surface.

15. The method of claim 14 wherein the removal of the conformal dielectric layer from the first vertical surface and the second vertical surface exposes the first vertical surface and the second vertical surface for epitaxial growth of the source/drain region.

16. The method of claim 12 wherein the first fin and the first gate structure are separated by a gap from a second fin and a second gate structure, the dielectric layer fills the space, and further comprising:

removing the dielectric layer from the first vertical surface and the second vertical surface with an anisotropic etching process.

17. The method of claim 16 wherein the conformal dielectric layer is deposited on the first vertical surface and the second vertical surface, the dielectric layer is removed by the anisotropic etching process from the gap without removing the dielectric spacer from the cavity, and further comprising:

before the source/drain region is epitaxially grown, removing the dielectric spacer from the cavity, the conformal dielectric layer from the first vertical surface, and the conformal dielectric layer from the second vertical surface.

18. The method of claim 16 wherein the removal of the conformal dielectric layer from the gap exposes the first vertical surface and the second vertical surface for epitaxial growth of the source/drain region.

19. The method of claim 16 wherein the dielectric layer is comprised of an organic planarization layer (OPL) material, and the conformal dielectric layer is comprised of silicon nitride.

20. The method of claim 16 wherein the dielectric layer is comprised of silicon dioxide, and the conformal dielectric layer is comprised of silicon nitride.