CONTROL CIRCUIT FOR SYNCHRONOUS RECTIFIER AND THE METHOD THEREOF

• US 20190020282A1
• Filed: 06/28/2018
• Published: 01/17/2019
• Est. Priority Date: 07/11/2017
• Status: Active Grant

• Current Assignee: Chengdu Monolithic Power Systems Company Limited (Monolithic Power Systems Incorporated)
• Original Assignee: Chengdu Monolithic Power Systems Company Limited (Monolithic Power Systems Incorporated)
• Inventors: Li, Hui, Miao, Lei, Wang, Siran, Feng, Lin
• Granted Patent: US 10,432,104 B2
• Time in Patent Office: Days
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 3/33592 having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A synchronous switching converter with an energy storage component and a synchronous rectifier coupled to the energy storage component, having: a secondary control circuit configured to receive a slew rate threshold adjusting signal and a voltage across the synchronous rectifier, and to provide a secondary control signal; wherein the secondary control circuit detects a slew rate of the voltage across the synchronous rectifier, and maintains the synchronous rectifier being off when the slew rate of the voltage across the synchronous rectifier is lower than a slew rate threshold.

Claims

1. A synchronous switching converter with an energy storage component and a synchronous rectifier coupled to the energy storage component, comprising:

a secondary control circuit having a first input terminal configured to receive a slew rate threshold adjusting signal, a second input terminal configured to receive a voltage across the synchronous rectifier, and an output terminal configured to provide a secondary control signal based on the slew rate threshold adjusting signal and the voltage across the synchronous rectifier to control the synchronous rectifier; and

wherein the secondary control circuit detects a slew rate of the voltage across the synchronous rectifier, and maintains the synchronous rectifier being off when the slew rate of the voltage across the synchronous rectifier is lower than a slew rate threshold.

2. The synchronous switching converter of claim 1, further comprising a secondary control chip, wherein the secondary control circuit is integrated in the secondary control chip, and the secondary control chip has a slew rate threshold adjusting pin configured to couple the first input terminal of the secondary control circuit to an off-chip component.

3. The synchronous switching converter of claim 1, wherein the secondary control circuit comprises:

an on control circuit having a first input terminal configured to receive the voltage across the synchronous rectifier, a second input terminal configured to receive the slew rate threshold adjusting signal, and an output terminal configured to provide an on control signal based on the voltage across the synchronous rectifier and the slew rate threshold adjusting signal;

an off control circuit having an input terminal configured to receive the voltage across the synchronous rectifier, and an output terminal configured to provide an off control signal based on the voltage across the synchronous rectifier; and

a logic circuit having a first input terminal configured to receive the on control signal, a second input terminal configured to receive the off control signal, and an output terminal configured to provide the secondary control signal based on the on control signal and the off control signal.

4. The synchronous switching converter of claim 3, wherein the on control circuit comprises:

a first comparator having a first input terminal configured to receive a first threshold, a second input terminal configured to receive the voltage across the synchronous rectifier, and an output terminal configured to provide a first comparison signal based on a comparison result of the voltage across the synchronous rectifier with the first threshold;

a second comparator having a first input terminal configured to receive the voltage across the synchronous rectifier, a second input terminal configured to receive a second threshold, and an output terminal configured to provide a second comparison signal based on a comparison result of the voltage across the synchronous rectifier with the second threshold;

a pulse circuit having an input terminal configured to receive the first comparison signal, an adjusting terminal configured to receive the slew rate threshold adjusting signal, and an output terminal configured to provide a pulse signal based on the first comparison signal and the slew rate threshold adjusting signal, wherein when the first comparison signal flips from a second voltage level to a first voltage level, the pulse signal has a pulse maintaining a time period, and wherein the time period could be adjusted by the slew rate threshold adjusting signal; and

a logic gate circuit having a first input terminal configured to receive the pulse signal, a second input terminal configured to receive the second comparison signal, and an output terminal configured to provide the on control signal based on a logic operation to the pulse signal and the second comparison signal.

5. The synchronous switching converter of claim 1, wherein the secondary control circuit comprises:

an on control circuit having an input terminal configured to receive the voltage across the synchronous rectifier, and an output terminal configured to provide an on control signal based on the voltage across the synchronous rectifier;

an off control circuit having an input terminal configured to receive the voltage across the synchronous rectifier, and an output terminal configured to provide an off control signal based on the voltage across the synchronous rectifier; and

a logic circuit having a first input terminal configured to receive the on control signal, a second input terminal configured to receive the off control signal, and an output terminal configured to provide the secondary control signal based on the on control signal and the off control signal.

6. The synchronous switching converter of claim 5, wherein the on control circuit comprises:

a first comparator having a first input terminal configured to receive a first threshold, a second input terminal configured to receive the voltage across the synchronous rectifier, and an output terminal configured to provide a first comparison signal based on a comparison result of the voltage across the synchronous rectifier with the first threshold;

a second comparator having a first input terminal configured to receive the voltage across the synchronous rectifier, a second input terminal configured to receive a second threshold, and an output terminal configured to provide a second comparison signal based on a comparison result of the voltage across the synchronous rectifier with the second threshold;

a pulse circuit having an input terminal configured to receive the first comparison signal, and an output terminal configured to provide a pulse signal based on the first comparison signal, wherein when the first comparison signal flips from a second voltage level to a first voltage level, the pulse signal has a pulse maintaining a preset time period; and

a logic gate circuit having a first input terminal configured to receive the pulse signal, a second input terminal configured to receive the second comparison signal, and an output terminal configured to provide the on control signal based on a logic operation to the pulse signal and the second comparison signal.

7. The synchronous switching converter of claim 6, further comprising a secondary control chip, wherein the secondary control circuit is integrated in the secondary control chip, and the secondary control chip has a slew rate threshold adjusting pin configured to couple the first input terminal of the first comparator to an off-chip component.

8. The synchronous switching converter of claim 6, further comprising a secondary control chip, wherein the secondary control circuit is integrated in the secondary control chip, and the secondary control chip has a slew rate threshold adjusting pin configured to couple the second input terminal of the second comparator to an off-chip component.

9. The synchronous switching converter of claim 1, further comprising a primary switch coupled to the energy storage component, and a primary control chip configured to control the primary switch.

10. A control method of a synchronous switching converter having an energy storage component and a synchronous rectifier coupled to the energy storage component, comprising:

detecting a slew rate of a voltage across the synchronous rectifier; and

keeping the synchronous rectifier being off when the slew rate of the voltage across the synchronous rectifier is lower than a slew rate threshold.

11. The control method of claim 10, wherein keeping the synchronous rectifier being off when the slew rate of the voltage across the synchronous rectifier is lower than a slew rate threshold comprises:

providing a pulse signal based on a comparison result of the voltage across the synchronous rectifier with a first threshold, wherein the pulse signal has pulses when the voltage across the synchronous rectifier decreases to the first threshold, and each pulse maintains for a time period;

providing a comparison signal based on a comparison result of the voltage across the synchronous rectifier with a second threshold; and

controlling the synchronous rectifier based on a logical operation to the pulse signal and the comparison signal, wherein the synchronous rectifier is turned on when the comparison signal indicates the voltage across the synchronous rectifier is lower than the second threshold during when the pulse signal has a pulse, otherwise, the synchronous rectifier is maintained being off.

12. The control method of claim 11, further comprising turning off the synchronous rectifier when the voltage across the synchronous rectifier increases to a third threshold.

13. The control method of claim 11, further comprising blocking the comparison signal before an off time of the synchronous rectifier reaches a preset minimum off time period.

14. The control method of claim 11, further comprising regulating the first threshold with an off-chip component.

15. The control method of claim 11, further comprising regulating the second threshold with an off-chip component.

16. The control method of claim 11, further comprising regulating the time period of the pulse of the pulse signal with an off-chip component.

17. A synchronous switching converter comprising:

an energy storage component;

a synchronous rectifier coupled to the energy storage component;

a secondary control circuit configured to receive a slew rate threshold adjusting signal and a voltage across the synchronous rectifier, and to provide a secondary control signal based on the slew rate threshold adjusting signal and the voltage across the synchronous rectifier to control the synchronous rectifier; and

an off-chip component configured to provide the slew rate threshold adjusting signal;

wherein the secondary control circuit detects a slew rate of the voltage across the synchronous rectifier, and maintains the synchronous rectifier being off when the slew rate of the voltage across the synchronous rectifier is lower than a slew rate threshold.

18. The synchronous switching converter of claim 17, wherein the synchronous rectifier and the secondary control circuit are integrated in a secondary control chip, and wherein the secondary control chip has a pin coupled to the off-chip component.

19. The synchronous switching converter of claim 17, wherein the secondary control circuit comprises:

an on control circuit having a first input terminal configured to receive the voltage across the synchronous rectifier, a second input terminal configured to receive the slew rate threshold adjusting signal, and an output terminal configured to provide an on control signal based on the voltage across the synchronous rectifier and the slew rate threshold adjusting signal;

an off control circuit having an input terminal configured to receive the voltage across the synchronous rectifier, and an output terminal configured to provide an off control signal based on the voltage across the synchronous rectifier; and

a logic circuit having a first input terminal configured to receive the on control signal, a second input terminal configured to receive the off control signal, and an output terminal configured to provide the secondary control signal based on the on control signal and the off control signal.

20. The synchronous switching converter of claim 19, wherein the on control circuit comprises:

a first comparator having a first input terminal configured to receive a first threshold, a second input terminal configured to receive the voltage across the synchronous rectifier, and an output terminal configured to provide a first comparison signal based on a comparison result of the voltage across the synchronous rectifier with the first threshold;

a second comparator having a first input terminal configured to receive the voltage across the synchronous rectifier, a second input terminal configured to receive a second threshold, and an output terminal configured to provide a second comparison signal based on a comparison result of the voltage across the synchronous rectifier with the second threshold;

a pulse circuit having an input terminal configured to receive the first comparison signal, an adjusting terminal configured to receive the slew rate threshold adjusting signal, and an output terminal configured to provide a pulse signal based on the first comparison signal and the slew rate threshold adjusting signal, wherein when the first comparison signal flips from a second voltage level to a first voltage level, the pulse signal has a pulse maintaining a time period, and wherein the time period could be adjusted by the slew rate threshold adjusting signal; and

a logic gate circuit having a first input terminal configured to receive the pulse signal, a second input terminal configured to receive the second comparison signal, and an output terminal configured to provide the on control signal based on a logic operation to the pulse signal and the second comparison signal.