Manufacturing Method of Array Substrate, Array Substrate and Display Apparatus

• US 20190074305A1
• Filed: 09/08/2017
• Published: 03/07/2019
• Est. Priority Date: 02/20/2017
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Inventors: Gong, Kui, Duan, Xianxue
• Granted Patent: US 10,553,624 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/13685 Top gates
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31127 Etching organic layers
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2221/1021 Pre-forming the dual damascene structure in a resist layer
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 : employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/1606 : Graphene
• CPC Class Codes: H01L 29/41733 : for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 : for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/45 : Ohmic electrodes
• CPC Class Codes: H01L 29/458 : for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66045 : Field-effect transistors
• CPC Class Codes: H01L 29/78636 : with supplementary region or layer for improving the flatness of the device
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A manufacturing method of an array substrate, an array substrate and a display apparatus are provided. The manufacturing method includes: providing a base substrate; sequentially forming an active layer and a first insulating layer that covers the active layer on the base substrate; performing one patterning process on the first insulating layer, so as to form a first through hole and a second through hole that expose the active layer in the first insulating layer, and form a first recess at a surface of the first insulating layer; forming a conductive layer on the patterned first insulating layer, with the conductive layer being filled in the first through hole, the second through hole and the first recess; conducting a grinding process to form a source electrode, a drain electrode and a pixel electrode are formed respectively.

Claims

1. A manufacturing method of an array substrate, comprising:

providing a base substrate;

sequentially forming an active layer and a first insulating layer that covers the active layer on the base substrate;

performing one patterning process on the first insulating layer, so as to form a first through hole and a second through hole that expose the active layer in the first insulating layer, and form a first recess at a surface of the first insulating layer;

forming a conductive layer on the patterned first insulating layer, with the conductive layer being filled in the first through hole, the second through hole and the first recess; and

conducting a grinding process to remove the conductive layer on the surface of the first insulating layer and retain the conductive layer in the first through hole, the second through hole and the first recess, whereby a source electrode, a drain electrode and a pixel electrode are formed respectively.

2. The manufacturing method of the array substrate claimed as claim 1, wherein forming the active layer comprises,

forming a graphene conductor layer on the base substrate;

and

conducting treatment on the graphene conductor layer, to control substitution of part of carbon atoms in the graphene conductor layer with atoms of a substitution element, thus converting the graphene conductor layer into a graphene-like semiconductor layer, whereby the active layer is formed on the base substrate.

3. The manufacturing method of the array substrate claimed as claim 2, wherein the graphene conductor layer includes a first area and a second area insulated from each other, and the first area is treated to form the active layer, and the second area is used for forming a gate line.

4. The manufacturing method of the array substrate claimed as claim 3, wherein the graphene conductor layer further includes a third area insulated from both the first area and the second area, and the third area is used for forming a common electrode.

5. The manufacturing method of the array substrate claimed as claim 2, wherein conducting treatment on the graphene conductor layer comprises:

coating a photoresist on the graphene conductor layer;

conducting exposure of the photoresist with a graytone mask or halftone mask, then performing development of exposed photoresist, so as to form a photoresist mask layer including a photoresist fully-retained region, a photoresist half-retained region and a photoresist fully-removed region;

etching the photoresist half-retained region so as to expose the graphene conductor layer;

controlling the substitution of part of carbon atoms in the graphene conductor layer with atoms of the substitution element under plasma condition;

wherein the substitution element is at least one of various elements including a fifth main group element, a sixth main group element, a seventh main group element and a lanthanide element; and

removing the photoresist.

6. The manufacturing method of the array substrate claimed as claim 1, further comprising:

before the first insulating layer is formed, forming a gate line on the base substrate;

in the first insulating layer, when the first through hole and the second through hole are formed, also forming a third through hole exposing the gate line and a second recess between the first through hole and the second through hole; and

after the grinding process is conducted, retaining the conductive layer in the second recess and the third through hole to form a gate electrode, which is electrically connected to the gate line via the third through hole.

7. The manufacturing method of the array substrate claimed as claim 1, further comprising:

forming a gate line and a gate electrode electrically connected to the gate line on the base substrate; and

forming a second insulating layer that covers the gate line and the gate electrode, wherein the active layer is formed on the second insulating layer.

8. The manufacturing method of the array substrate claimed as claim 6, further comprising:

forming a common electrode simultaneous with formation of the gate line.

9. The manufacturing method of the array substrate claimed as claim 1, further comprising:

forming a passivation layer to cover the source electrode, the drain electrode and the pixel electrode, and

forming a common electrode on the passivation layer.

10. The manufacturing method of the array substrate claimed as claim 1, further comprising:

forming a third recess at the surface of the first insulating layer, and retaining the conductive layer in the third recess to form a common electrode.

11. The manufacturing method of the array substrate claimed as claim 1, wherein the one pattering process comprises:

coating a photoresist on the first insulating layer;

conducting exposure on the photoresist with a graytone mask or halftone mask, then performing development of exposed photoresist so as to form a photoresist mask layer including a photoresist fully-retained region, a photoresist half-retained region and a photoresist fully-removed region;

forming a first blind hole and a second blind hole with a first etching process;

removing the photoresist in the photoresist half-retained region with an ashing process;

forming the first recess as well as the first through hole and the second through hole that expose the active layer at locations of the first blind and the second blind hole with a second etching process, the first through hole being a stepped hole including a first portion and a second portion, the second through hole being a stepped hole including a third portion and a fourth portion; and

removing the photoresist.

12. The manufacturing method of the array substrate claimed as claim 1, wherein the grinding process is a chemical mechanical polishing process, and after the grinding process is conducted on the first insulating layer with the conductive layer deposited thereon, a flat surface is obtained.

13. An array substrate, comprising:

a base substrate;

an active on the base substrate and a first insulating layer covering the active layer, the first insulating layer having a first through hole and a second through hole that expose the active layer and a first recess at a surface of the first insulating layer;

a source electrode and a drain electrode that are located in the first through hole and the second through hole in the first insulating layer, respectively, and connected to the active layer, and a pixel electrode in the first recess.

14. The array substrate claimed as claim 13, wherein the active layer is a graphene-like semiconductor layer formed by controlling substitution of part of carbon atoms in a graphene conductor layer with atoms of a substitution element, and the substitution element is at least one of various elements including a fifth main group element, a sixth main group element, a seventh main group element and a lanthanide element.

15. The array substrate claimed as claim 13, further comprising:

a gate line covered by the first insulating layer;

a third through hole that is in the first insulating layer and exposes the gate line and a second recess at a surface of the first insulating layer; and

a gate electrode in the second recess and the third through hole;

wherein the gate electrode is electrically connected to the third through hole and the gate line.

16. The array substrate claimed as claim 13, further comprising:

a gate line on the base substrate and a gate electrode electrically connected to the gate line; and

a second insulating layer covering the gate line and the gate electrode;

wherein the active layer is on the second insulating layer.

17. The array substrate claimed as claim 13, further comprising:

a common electrode on the base substrate;

wherein the common electrode is covered by the first insulating layer.

18. The array substrate claimed as claim 13, further comprising:

a passivation layer covering the source electrode, the drain electrode and the pixel electrode; and

a common electrode on the passivation layer.

19. The array substrate claimed as claim 13, further comprising:

a third recess at the surface of the first insulating layer; and

a common electrode in the third recess.

20. A display apparatus, comprising the array substrate claimed as claim 13.