HALL EFFECT SENSOR WITH ENHANCED SENSITIVITY AND METHOD FOR PRODUCING THE SAME

• US 20190097126A1
• Filed: 11/26/2018
• Published: 03/28/2019
• Est. Priority Date: 08/01/2017
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: TAN, Shyue Seng, TOH, Eng Huat
• Granted Patent: US 10,707,408 B2
• Time in Patent Office: Days
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 52/01 Manufacture or treatment
• CPC Class Codes: H10N 52/101 Semiconductor Hall-effect devices
• CPC Class Codes: H10N 52/80 Constructional details
• CPC Class Codes: H10N 59/00 Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00 MRAM devices H10B61/00

Abstract

Methods of forming a high sensitivity Hall effect sensor having a thin Hall plate and the resulting devices are provided. Embodiments include providing a SOI substrate having a sequentially formed Si substrate and BOX and Si layers; forming a first STI structure in a first portion of the Si layer above the BOX layer, the first STI structure having a cross-shaped pattern; forming a second STI structure in a frame-shaped pattern in a second portion of the Si layer; the second STI structure formed outside and adjacent to the first STI structure; removing a portion of the Si layer between the first and second STI structures down to the BOX layer; removing the first STI structure, a cross-shaped Si layer remaining; and implanting N+ dopant ions into each end of the cross-shaped Si layer to form N+ implantation regions.

Claims

1. A device comprising:

a shallow trench isolation (STI) structure formed in a frame-shaped pattern through a silicon (Si) layer to a buried oxide (BOX) layer of a silicon-on-insulator (SOI) substrate;

a cross-shaped Si layer over the BOX layer, the cross-shaped Si layer within and adjacent to the frame-shaped STI structure; and

N+ type ion-doped implantation regions at opposite ends of the cross-shaped Si layer.

2. The device according to claim 1, wherein the cross-shaped Si layer has a thickness of 100 angstrom (Å

) to 1000 Å

.

3. The device according to claim 1, wherein the BOX layer has a thickness of 140 nanometer (nm) to 200 nm.

4. The device according to claim 1, wherein the BOX layer is an ultra-thin buried oxide (UTBOX) layer having a thickness of 10 nm to 30 nm.

5. The device according to claim 1, further comprising a front and a back gate over opposite sides of the cross-shaped Si layer.

6. A device comprising:

an isolation structure formed in a frame-shaped pattern through a silicon (Si) layer to an oxide layer of a silicon-on-insulator (SOI) substrate;

a cross-shaped Si layer over the oxide layer, the cross-shaped Si layer within and adjacent to the frame-shaped isolation structure; and

ion-doped implantation regions at opposite ends of the cross-shaped Si layer.

7. The device according to claim 6, wherein the cross-shaped Si layer has a thickness of 100 angstrom (Å

) to 1000 Å

.

8. The device according to claim 6, wherein the oxide layer comprises a buried oxide (BOX) layer.

9. The device according to claim 8, wherein the BOX layer has a thickness of 140 nanometer (nm) to 200 nm.

10. The device according to claim 8, wherein the BOX layer is an ultra-thin buried oxide (UTBOX) layer having a thickness of 10 nm to 30 nm.

11. The device according to claim 6, further comprising a front and a back gate over opposite sides of the cross-shaped Si layer.

12. The device according to claim 6, wherein the isolation structure comprises shallow trench isolation (STI) structure.

13. The device according to claim 6, wherein the ion doped implantation regions comprise N+ type ion-doped implantation regions at the opposite ends of the cross-shaped Si layer.

14. The device according to claim 13, wherein an n-type dopant is implanted on the cross-shaped Si layer prior to implanting the N+ dopant ions.

15. The device according to claim 6, wherein the SOI substrate comprises a partially-depleted silicon-on-insulator (PDSOI).

16. The device according to claim 6, further comprising a front and a back gate formed on opposite sides of the cross-shaped Si layer.

17. A device comprising:

a silicon-on-insulator (SOI) substrate having a sequentially formed silicon (Si) substrate and an ultra-thin buried oxide (UTBOX) and Si layers;

a shallow trench isolation (STI) structure formed in a frame-shaped pattern through a silicon (Si) layer to the UTBOX layer;

a cross-shaped Si layer over the UTBOX layer, the cross-shaped Si layer within and adjacent to STI structure; and

N+ dopant ions implanted into opposite ends of the cross-shaped Si layer to form N+ implantation regions.

18. The device according to claim 17, wherein the SOI substrate comprises a partially-depleted silicon-on-insulator (PDSOI).

19. The device according to claim 18, wherein the UTBOX layer has a thickness of 10 nanometer (nm) to 30 nm.

20. The device according to claim 18, wherein an n-type dopant on the cross-shaped Si layer is implanted prior to the N+ dopant ion implantation.