SEMICONDUCTOR PACKAGE

• US 20200135631A1
• Filed: 10/23/2019
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: SEO, Young Kwan, CHAE, Seung Hun, MOON, So Yeon
• Application Number:
  US16/661,585
• Publication Number:
  US 20200135631A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 23/053 the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures

Abstract

A semiconductor package includes a semiconductor chip having a connection pad; an encapsulant covering at least a portion of the semiconductor chip; and an interconnect structure disposed on the semiconductor chip and the encapsulant. The interconnect structure includes a first insulating layer, a first redistribution layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, the first redistribution layer is electrically connected to the connection pad, and when a thickness of the first redistribution layer is a, and a gap between patterns of the first redistribution layer is b, b/a is 4 or less.

Claims

1. A semiconductor package, comprising:

a semiconductor chip having a connection pad;

an encapsulant covering at least a portion of the semiconductor chip; and

an interconnect structure disposed on the semiconductor chip and the encapsulant,

wherein the interconnect structure includes a first insulating layer, a first redistribution layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and covering the first redistribution layer,

wherein the first redistribution layer is electrically connected to the connection pad, and

wherein b/a is 4 or less, in which a is thickness of the first redistribution layer, and b is a gap between patterns of the first redistribution layer.

2. The semiconductor package of claim 1, wherein b/a is 0.1 or greater.

3. The semiconductor package of claim 1, wherein a is 10 μ

m or less.

4. The semiconductor package of claim 3, wherein a is 0.5 μ

m or greater.

5. The semiconductor package of claim 4, wherein b is 0.1 μ

m to 40 μ

m.

6. The semiconductor package of claim 1, wherein (c−

a)/a is 0.5 or greater, in which c is a sum of a thickness of the second insulating layer in a region covering the first redistribution layer and a thickness of the first redistribution layer covered by the region of the second insulating layer.

7. The semiconductor package of claim 6, wherein (c−

a)/a is 1.5 or less.

8. The semiconductor package of claim 7, wherein c is 1 μ

m to 20 μ

m.

9. The semiconductor package of claim 1, wherein the first redistribution layer includes copper (Cu).

10. The semiconductor package of claim 1, wherein the second insulating layer includes a photosensitive insulating material (PID).

11. The semiconductor package of claim 1, wherein a sum of a thickness of the second insulating layer in a region covering the first redistribution layer and a thickness of the first redistribution layer covered by the region of the second insulating layer is greater than a thickness of the second insulating layer in a region between patterns of the first redistribution layer.

12. The semiconductor package of claim 11, wherein (c−

d)/c is 0.5 or less, in which c is the sum of the thickness of the second insulating layer in the region covering the first redistribution layer and the thickness of the first redistribution layer covered by the region of the second insulating layer, and d is the thickness of the second insulating layer in the region between the patterns of the first redistribution layer.

13. The semiconductor package of claim 1, wherein the interconnect structure further includes a second redistribution layer disposed on the second insulating layer.

14. The semiconductor package of claim 1, further comprising:

a frame having a through-hole,

wherein the semiconductor chip is disposed in the through-hole, and

wherein the encapsulant fills at least a portion of the through-hole.

15. The semiconductor package of claim 14,

wherein the frame includes a first built-up layer in contact with the first insulating layer, a first wiring layer in contact with the first insulating layer and buried in the first built-up layer, a second wiring layer disposed on a portion of the first built-up layer opposing a portion in which the first wiring layer is buried, a second built-up layer disposed on the first built-up layer and covering the second wiring layer, and a third wiring layer disposed on a portion of the second built-up layer opposing a portion in which the second wiring layer is buried, and

wherein the first to third wiring layers are electrically connected to the connection pad.

16. The semiconductor package of claim 14,

wherein the frame further includes a core layer, first and second wiring layers disposed on both surfaces of the core layer, respectively, first and second built-up layers disposed on both surfaces of the core layer, respectively, and covering the first and second wiring layers, respectively, a third wiring layer disposed on a portion of the first built-up layer opposing a portion in which the first wiring layer is buried, and a fourth wiring layer disposed on a portion of the second built-up layer opposing a portion in which the second wiring layer is buried, and

wherein the first to fourth wiring layers are electrically connected to the connection pad.