Semiconductor device, microcomputer and flash memory

• US 6,643,193 B2
• Filed: 09/20/2002
• Issued: 11/04/2003
• Est. Priority Date: 09/04/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Systems Company Limited (Hitachi, Ltd.)
• Inventors: Hirakii, Mitsuru, Tanaka, Toshihiro, Yamaki, Takashi, Fujito, Masamichi, Takeuchi, Kan, Shinagawa, Yutaka
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US10/247,301
• Publication Number:
  US 20030016566A1
• Time in Patent Office: 410 Days
• Field of Search: 365/189.09, 365/226, 365/189.01, 365/185.21, 365/225, 365/185.33
• US Class Current: 365/189.09
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance

Abstract

A semiconductor device whose characteristics are highly reliably regulated for circuits whose desired characteristics need to be realized without being affect by unevenness in device characteristics is to be provided. A replica MOS transistor for amperage measurement connected to an external measuring terminal is provided. A delay circuit and other circuits whose desired characteristics are to be realized have a constant current source MOS transistor formed in the same process as the replica MOS transistor, and a trimming voltage vtri is commonly applied to the respective gates of the constant current source MOS transistor and the replica MOS transistor. Trimming data determined on the basis of an amperage measured from the external measuring terminal are stored into a memory means such as an electrically rewritable non-volatile memory or the like. The trimming data determine the trimming voltage vtri.

Claims

1. A semiconductor integrated circuit, comprising:

a memory circuit which holds control data;

a voltage generating circuit which generates a control voltage in accordance with the control data;

a plurality of circuits each of which includes a current source circuit generating a reference current in accordance with the control voltage;

a signal line coupled to the voltage generating circuit to commonly provide the control voltage to the respective current source;

a measuring transistor having a control terminal coupled to the signal line and a current terminal; and

an external terminal which is coupled to the current terminal of the measuring transistor and which makes possible external measurement of a current flowing through the measuring transistor.

2. A semiconductor integrated circuit according to claim 1,

wherein the current source circuit includes a current source MOS transistor receiving the control voltage at a control terminal and subjected to the control of mutual conductance.

3. A semiconductor integrated circuit according to claim 2, further comprising:

a non-volatile memory element whose threshold voltage is electrically changeable;

a control circuit which controls change of the threshold voltage of the non-volatile memory element; and

a sense amplifier which detects whether or not the change of the threshold voltage by the control circuit has been completed,

wherein the sense amplifier includes;

a logic gate having a predetermined logic threshold voltage coupled to a data terminal of the non-volatile memory element;

the current source circuit having the current source MOS transistor and generating a predetermined voltage in accordance with the current flowing through the current source MOS transistor; and

a load MOS transistor coupled to receive the voltage generated by the current source circuit and subjected to mutual conductance control, the load MOS transistor supplying a current to the data terminal of the non-volatile memory element and controlling an input of the logic gate to a voltage in the vicinity of the logic threshold voltage when the threshold voltage of the non-volatile memory element has reached a predetermined state.