Semiconductor wafer with process control modules

• US 6,680,523 B2
• Filed: 02/21/2002
• Issued: 01/20/2004
• Est. Priority Date: 02/27/2001
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Hubmer, Paul, Schober, Joachim H., Scheucher, Heimo
• Primary Examiner(s): Talbott, David L.
• Assistant Examiner(s): THAI, LUAN C
• Application Number:
  US10/081,893
• Publication Number:
  US 20020117735A1
• Time in Patent Office: 698 Days
• Field of Search: 257/620, 257/48
• US Class Current: 257/620
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A semiconductor wafer (1) has a multitude of chips (5), of which chips (5) each one of a given number of chips (5) is situated in one of a multitude of adjacent exposure fields (2), and further has process control modules (4) which are each arranged in an exposure field (2), namely each in place of at least one chip (5).

Claims

1. A semiconductor wafer (1) having a multitude of chips (5), of which chips (5) each one of a given number of chips (5) is situated in one of a multitude of adjacent exposure fields (2), and having process control modules (4) which are each arranged in a given area on the semiconductor wafer (1), in which the given areas are formed by the exposure fields (2), and in which each process control module (4) takes the place of at least one chip (5).

2. A semiconductor wafer (1) as claimed in claim 1, in which a process control module (4) is present in each one of at least 25% of all the exposure fields (2), and in which the process control modules (4) are situated at equal distances from each other with respect to two mutually perpendicular coordinate directions (7, 8).

3. A semiconductor wafer (1) as claimed in claim 2, in which a process control module (4) is present in each exposure field (2).

4. A semiconductor wafer (1) as claimed in claim 1, in which all the process control modules (4) are each situated at the same location (6) in the respective exposure fields (2).