Clock synchronous semiconductor memory device

  • US 6,697,296 B2
  • Filed: 05/09/2002
  • Issued: 02/24/2004
  • Est. Priority Date: 06/13/2001
  • Status: Active Grant
First Claim
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1. A semiconductor device comprising:

  • a plurality of input buffers of different types or configurations from each other and coupled to a common internal node; and

    program circuitry for generating a signal setting one of said plurality of input buffers to an operable state, said plurality of input buffers driving the internal node according to a received signal when an input buffer is set to the operable state.

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