System for validating and monitoring semiconductor testing tools

• US 6,724,211 B2
• Filed: 09/12/2001
• Issued: 04/20/2004
• Est. Priority Date: 04/30/2001
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Ming-Hui, Wang, Chun-Sheng, Liu, Yao-Tung, Cheng, Yung-Min, Lin, Li-Chung, Chen, Hsin-Hom, Chen, Shun-An
• Primary Examiner(s): Zarneke, David A.
• Assistant Examiner(s): TANG, MINH NHUT
• Application Number:
  US09/949,656
• Publication Number:
  US 20020158624A1
• Time in Patent Office: 951 Days
• Field of Search: 324/73.1, 324/754, 324/760, 324/763, 324/765, 324/768, 324/158.1, 714/724, 702/117-119, 702/123
• US Class Current: 324/750.02
• CPC Class Codes: G06F 11/2294 by remote test

Abstract

A system for monitoring semiconductor testing tools comprises a tester testing a semiconductor device, whereby a test result is derived, a storage device storing a logic function corresponding to the semiconductor device, and a processor receiving the test result and the logic function from the tester and storage device respectively, and applying the logic function to the test result for validation.

Claims

1. A system for monitoring semiconductor testing tools comprising:

a tester testing a semiconductor device, whereby a test result is derived;

a storage device storing a logic function corresponding to the semiconductor device; and

a processor receiving the test result and the logic function from the tester and the storage device respectively, and applying the logic function to the test result for validation of the tester.

2. The system as claimed in claim 1 wherein the semiconductor device is a wafer having dices thereon.

3. The system as claimed in claim 1 wherein the storage device further stores an action implemented by the tester when the validation is failed.

4. The system as claimed in claim 3 wherein the action is to re-test.

5. The system as claimed in claim 3 wherein the action is to stop testing.

6. The system as claimed in claim 3 wherein the action is to alarm.

7. The system as claimed in claim 1 further comprising an input device connected to the storage device.

8. The system as claimed in claim 1 further comprising a display connected to the storage device.

9. The system as claimed in claim 1 wherein the processor communicates with the tester through a SECS tool link.

10. A system for validating semiconductor test tools using a semiconductor device which a first test result has been derived from and validated, the system comprising:

a tester testing the semiconductor device, whereby a second test result is derived;

a storage device storing the first test result of the semiconductor device;

a processor receiving the first and second test result from the storage device and the tester respectively, and comparing the first and second test result for validation of the second test result;

a tool controller controlling the tester and receiving the second test result from the tester; and

a setup server receiving the first and second test result from the storage device and the tool controller respectively, and comparing the first and the second test result.

11. The system as claimed in claim 10 wherein the semiconductor device is a wafer having dices thereon.

12. The system as claimed in claim 11 wherein the storage device further stores a selection rule and the dices are selectively tested according to the selection rule.

13. The system as claimed in claim 11 wherein the storage device further stores life times of the dices.

14. The system as claimed in claim 10 wherein the storage device further stores an action implemented by the tester when the validation is failed.

15. The system as claimed in claim 14 wherein the action is to re-test.

16. The system as claimed in claim 14 wherein the action is to stop testing.

17. The system as claimed in claim 14 wherein the action is to alarm.

18. The system as claimed in claim 10 wherein the processor communicates with the tester through a SECS tool link.

19. The system as claimed in claim 10 further comprising a display connected to the storage device.

20. The system as claimed in claim 10 further comprising an input device connected to the storage device.

21. A system for validating semiconductor test tools using a semiconductor device which a first test result has been derived from and validated, the system comprising:

a tester testing the semiconductor device, whereby a second test result is derived;

a storage device storing the first test result of the semiconductor device; and

a processor receiving the first and second test result from the storage device and the tester respectively, and comparing the first and second test result for validation of the tester.

22. The system as claimed in claim 21 wherein the semiconductor device is a wafer having dice;

thereon.

23. The system as claimed in claim 22 wherein the storage device further stores a selection rule and the dices are selectively tested according to the selection rule.

24. The system as claimed in claim 22 wherein the storage device further stores life times of the dices.

25. The system as claimed in claim 21 wherein the storage device further stores an action implemented by the tester when the validation is failed.

26. The system as claimed in claim 25 wherein the action is to re-test the semiconductor device.

27. The system as claimed in claim 25 wherein the action is to stop testing.

28. The system as claimed in claim 25 wherein the action is to alarm.

29. The system as claimed in claim 21 further comprising:

a tool controller controlling the tester and receiving the second test result from the tester;

a setup server receiving the first and second test result from the storage device and the tool controller respectively, and comparing the first and the second test result.

30. The system as claimed in claim 29 wherein the processor communicates with the tester through a SECS tool link.

31. The system as claimed in claim 21 further comprising a display connected to the storage device.

32. The system as claimed in claim 21 further comprising an input device connected to the storage device.