Method of manufacturing chip scale package

• US 6,735,859 B2
• Filed: 12/09/2002
• Issued: 05/18/2004
• Est. Priority Date: 02/23/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Corsis, David J.
• Primary Examiner(s): Arbes, Carl J.
• Assistant Examiner(s): Phan, Tim
• Application Number:
  US10/315,527
• Publication Number:
  US 20030084566A1
• Time in Patent Office: 526 Days
• Field of Search: 298/54, 298/27, 298/30, 298/32, 298/40, 257/666, 257/676, 257/677, 257/787, 361/709, 361/719
• US Class Current: 29/854
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 23/3672 Foil-like cooling fins or heat sinks being part of lead-frames H01L23/49568
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49568 specifically adapted to facilitate heat dissipation
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: Y10T 29/49004 : including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49121 : Beam lead frame or beam lead device
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49169 : Assembling electrical component directly to terminal or elongated conductor

Abstract

A dense semiconductor flip-chip device assembly is provided with a heat sink/spreading/dissipating member which is formed as a paddle of a metallic paddle frame in a strip of paddle frames. Dice are bonded to the paddles by e.g. conventional die attach methods, enabling bump attachment and testing to be conducted before detachment from the paddle frame strip.

Claims

1. A method of assembly for a chip scale package, said chip scale package having a semiconductor die having an active surface having one of a plurality of bond pads thereon and a plurality of bond pads having conductive projections thereon and an opposing second surface and having a metallic paddle frame having left and right side rails and having a paddle located therebetween, comprising:

attaching said opposing second surface of said semiconductor die to said paddle for use of said paddle as a heat sink for said semiconductor die; and

disconnecting said paddle having said semiconductor die attached thereto from said metallic paddle frame.

2. The method of claim 1, further comprising:

testing said semiconductor die for electrical properties while said paddle is located between said side rails of said metallic paddle frame.

3. The method of claim 1, further comprising:

providing a substrate, said substrate comprising a printed circuit board having a plurality of circuits thereon; and

connecting said plurality of bond pads of said semiconductor die to said plurality of circuits of said printed circuit board.

4. The method of claim 1, wherein said semiconductor die is attached to said paddle by an electrically non-conductive adhesive material.

5. The method of claim 4, wherein said electrically non-conductive adhesive material comprises a polymer.

6. The method of claim 4, wherein said electrically non-conductive adhesive material comprises one of polyimide and epoxy.

7. The method of claim 4, wherein said electrically non-conductive adhesive material comprises a polyimide tape.

8. The method of claim 1, wherein said opposing second surface of said semiconductor die is attached to said paddle by an electrically conductive material.

9. The method of claim 8, wherein said electrically conductive material comprises a eutectic material.

10. The method of claim 9, wherein said eutectic material comprises a gold-silicon eutectic layer.

11. The method of claim 8, wherein said electrically conductive material comprises a polymer filled with conductive particles.

12. The method of claim 1, further comprising:

providing a plurality of conductive bumps on said plurality of bond pads on said active surface of said semiconductor die for conductive ball-grid-array connection to a substrate.

13. The method of claim 1, further comprising:

providing a substrate having a plurality of circuits thereon; and

correcting said plurality of bond pads on said active surface of said semiconductor die by a conductive ball-grid-array connection to said plurality of circuits on said substrate.

14. The method of claim 13, wherein said substrate is connected to said plurality of bond pads on said active surface of said semiconductor die by said conductive ball-grid-array connection to said substrate.