Low ohmic layout technique for MOS transistors

• US 7,112,855 B2
• Filed: 05/07/2004
• Issued: 09/26/2006
• Est. Priority Date: 05/07/2004
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Fong, Victor
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US10/840,602
• Publication Number:
  US 20050250300A1
• Time in Patent Office: 872 Days
• Field of Search: 257/382, 257/383, 257/384, 257/385
• US Class Current: 257/382
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The disclosure relates to a transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first and second interconnect layers are formed on top of the substrate. A first plurality of contacts connect the source regions to one of the first or second interconnect layers. A second plurality of contacts connect the drain regions to the other of the first or second interconnect layers. The first and second interconnect layers cover a region above the substrate area in which the plurality of transistors reside so as to achieve a low ohmic result. The second interconnect layer has openings therein for one of the respective first or second plurality of contacts to pass therethrough and couple to the at least one first interconnect layer. Either the first or second interconnect layers can function as an input or output for the circuit.

Claims

1. A circuit, comprising:

(a) a plurality of transistors, each with source and drain regions formed in a substrate;

(b) a first interconnect layer formed on top of said substrate;

(c) a second interconnect layer formed on top of said substrate;

(d) a first plurality of contacts connecting said source regions to one of said first or second interconnect layers; and

(e) a second plurality of contacts connecting said drain regions to the other of said first or second interconnect layers;

wherein said first interconnect layer occupies a region above said substrate area in which the plurality of transistors reside, and

wherein said second interconnect layer is located above said plurality of transistors and has openings therein for one of said respective first or second plurality of contacts to pass therethrough and couple to said at least one first interconnect layer.

2. The circuit of claim 1, further comprising slots in said first interconnect layer.

3. The circuit of claim 1, further comprising slots in said second interconnect layer.

4. The circuit of claim 1, further comprising an input coupled to said first interconnect layer and an output coupled to said second interconnect layer.

5. The circuit of claim 1, further comprising an input coupled to said second interconnect layer and an output coupled to said first interconnect layer.

6. The circuit of claim 1, wherein said plurality of transistors comprise metal oxide semiconductors transistors.

7. The circuit of claim 1, wherein said plurality of transistors comprise complementary metal oxide semiconductors transistors.

8. The circuit of claim 1, wherein said first and second interconnect layers comprise at least one of metal, metal alloy and polycrystalline silicon.

9. The circuit of claim 1, wherein said first interconnect layer is connected to at least one further metal, metal alloy or polysilicon layer.

10. The circuit of claim 1, wherein said second interconnect layer is connected to at least one further metal, metal alloy or polysilicon layer.

11. The circuit of claim 1, wherein said first interconnect layer covers a substantial portion of said regions.

12. The circuit of claim 1, wherein said second interconnect layer covers a substantial portion of said regions.