Configurable real-time trace port for embedded processors

  • US 7,149,926 B2
  • Filed: 05/22/2003
  • Issued: 12/12/2006
  • Est. Priority Date: 05/22/2003
  • Status: Active Grant
First Claim
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1. An embedded processor comprising:

  • a processor core for executing a program instruction associated with an instruction word transmitted on an instruction bus, and for transmitting a corresponding data word on a data bus in response to the executed program instruction; and

    a trace port circuit including;

    a configurable filter circuit coupled to the instruction bus and the data bus for selectively passing at least a portion of the instruction word and the corresponding data word when at least one of the instruction word and the corresponding data word satisfies a user-defined trigger event;

    a compression circuit for compressing said at least one of the instruction word and the corresponding data word passed from the configurable filter circuit; and

    an output buffer for temporarily storing the compressed instruction word and compressed data word,wherein the configurable filter circuit includes a first trace filter including a switch having input terminals connected to the instruction bus and the data bus,wherein the embedded processor further comprises a on-chip debug support (OCDS) circuit coupled to the instruction bus and the data bus, the OCDS circuit including storage that stores instruction information and data information, and a generator that generates a switch control signal that causes the first switch to pass said portion of the instruction word and the corresponding data word when at least one of the instruction word and the corresponding data word matches the stored instruction information and data information, andwherein the OCDS circuit comprises;

    programmable trigger generator including;

    a plurality of trigger event detection registers, each said register including a memory circuit for storing at least one trigger value, and an assertor that asserts a pre-trigger signal only when the stored trigger value matches a corresponding value transmitted on at least one of the data address bus, the data value bus, and the instruction bus, anda programmable trigger logic circuit including a function generator for generating an intermediate trigger signal in response to a user-defined combination of the pre-trigger signals generated by the plurality of trigger event detection registers; and

    an action generator circuit for asserting a BWP trigger in response to the intermediate trigger signal.

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