Configurable real-time trace port for embedded processors
DCFirst Claim
1. An embedded processor comprising:
- a processor core for executing a program instruction associated with an instruction word transmitted on an instruction bus, and for transmitting a corresponding data word on a data bus in response to the executed program instruction; and
a trace port circuit including;
a configurable filter circuit coupled to the instruction bus and the data bus for selectively passing at least a portion of the instruction word and the corresponding data word when at least one of the instruction word and the corresponding data word satisfies a user-defined trigger event;
a compression circuit for compressing said at least one of the instruction word and the corresponding data word passed from the configurable filter circuit; and
an output buffer for temporarily storing the compressed instruction word and compressed data word,wherein the configurable filter circuit includes a first trace filter including a switch having input terminals connected to the instruction bus and the data bus,wherein the embedded processor further comprises a on-chip debug support (OCDS) circuit coupled to the instruction bus and the data bus, the OCDS circuit including storage that stores instruction information and data information, and a generator that generates a switch control signal that causes the first switch to pass said portion of the instruction word and the corresponding data word when at least one of the instruction word and the corresponding data word matches the stored instruction information and data information, andwherein the OCDS circuit comprises;
programmable trigger generator including;
a plurality of trigger event detection registers, each said register including a memory circuit for storing at least one trigger value, and an assertor that asserts a pre-trigger signal only when the stored trigger value matches a corresponding value transmitted on at least one of the data address bus, the data value bus, and the instruction bus, anda programmable trigger logic circuit including a function generator for generating an intermediate trigger signal in response to a user-defined combination of the pre-trigger signals generated by the plurality of trigger event detection registers; and
an action generator circuit for asserting a BWP trigger in response to the intermediate trigger signal.
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Abstract
An embedded processor having a programmable trace port that selectively limits the amount of trace information passed from the processor core to an output buffer, and selectively controls the rate at which the trace information is output from the output buffer to an off-chip debug system. A configurable on-chip filter circuit selectively passes data and program information based on a wide range of user-defined combinations and/or sequences of trigger events (e.g., instruction addresses/types or data addresses/values). The filtered trace information is then compressed using separate data and program compression circuits, and passed to separate data and program output buffer. The data output buffer includes an adjustable read (output) rate (e.g., one-half or one-quarter of the processor core clock cycle), and allows a user to select between one or two output pointers.
51 Citations
21 Claims
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1. An embedded processor comprising:
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a processor core for executing a program instruction associated with an instruction word transmitted on an instruction bus, and for transmitting a corresponding data word on a data bus in response to the executed program instruction; and a trace port circuit including; a configurable filter circuit coupled to the instruction bus and the data bus for selectively passing at least a portion of the instruction word and the corresponding data word when at least one of the instruction word and the corresponding data word satisfies a user-defined trigger event; a compression circuit for compressing said at least one of the instruction word and the corresponding data word passed from the configurable filter circuit; and an output buffer for temporarily storing the compressed instruction word and compressed data word, wherein the configurable filter circuit includes a first trace filter including a switch having input terminals connected to the instruction bus and the data bus, wherein the embedded processor further comprises a on-chip debug support (OCDS) circuit coupled to the instruction bus and the data bus, the OCDS circuit including storage that stores instruction information and data information, and a generator that generates a switch control signal that causes the first switch to pass said portion of the instruction word and the corresponding data word when at least one of the instruction word and the corresponding data word matches the stored instruction information and data information, and wherein the OCDS circuit comprises; programmable trigger generator including; a plurality of trigger event detection registers, each said register including a memory circuit for storing at least one trigger value, and an assertor that asserts a pre-trigger signal only when the stored trigger value matches a corresponding value transmitted on at least one of the data address bus, the data value bus, and the instruction bus, and a programmable trigger logic circuit including a function generator for generating an intermediate trigger signal in response to a user-defined combination of the pre-trigger signals generated by the plurality of trigger event detection registers; and an action generator circuit for asserting a BWP trigger in response to the intermediate trigger signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. An embedded processor comprising:
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a processor core for executing a program instruction associated with an instruction word transmitted on an instruction bus, and for transmitting a corresponding data word on a data bus in response to the executed program instruction; and a trace port circuit including; a configurable filter circuit coupled to the instruction bus and the data bus for selectively passing at least a portion of the instruction word and the corresponding data word when at least one of the instruction word and the corresponding data word satisfies a user-defined trigger event; a compression circuit for compressing said at least one of the instruction word and the corresponding data word passed from the configurable filter circuit; and an output buffer for temporarily storing the compressed instruction word and compressed data word, wherein the configurable filter circuit further includes a first trace filter having a first switch connected between a first intermediate bus and a first output bus, a second switch connected between a second intermediate bus and a second output bus, and third switch connected between a third intermediate bus and a third output bus, wherein the first, second and third intermediate busses are connected to corresponding output terminals of the first trace filter, and wherein the first, second and third output busses are connected to the compression circuit. - View Dependent Claims (19, 20)
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21. An embedded processor comprising:
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a processor core for executing a program instruction associated with an instruction word transmitted on an instruction bus, and for transmitting a corresponding data word on a data bus in response to the executed program instruction; and a trace port circuit including; a configurable filter circuit coupled to the instruction bus and the data bus for selectively passing at least a portion of the instruction word and the corresponding data word when at least one of the instruction word and the corresponding data word satisfies a user-defined trigger event; a compression circuit for compressing said at least one of the instruction word and the corresponding data word passed from the configurable filter circuit; and an output buffer for temporarily storing the compressed instruction word and compressed data word, wherein each data word includes a data address transmitted on a first portion of the data bus, and a data value transmitted on a second portion of the data bus, and wherein the compression circuit comprises; a converter that converts the data value and the data address into at least one data trace words according to a predetermined compression scheme, and for transmitting the at least one data trace words to the output buffer; and a generator that generates at least one identification codes, each identification code being transmitted with a corresponding data trace word, wherein the output buffer comprises a second First-In-First-Out (FIFO) circuit including; a plurality of sequentially arranged registers; a write pointer circuit for sequentially writing the at least one data trace words into the sequentially arranged registers at a processor core frequency; and a read pointer/driver circuit for sequentially reading data trace words from the sequentially arranged registers at a user-defined frequency, and for driving the read program trace bytes onto a second set of device pins, and wherein the read pointer circuit further comprises an adjuster that adjusts between a first control state in which one data trace word is read and driven onto the second set of device pins during each clock cycle of the user-defined frequency, and a second control state in which a first data trace word is read from a first register and driven onto the second set of device pins, and a second data trace word is read from a second register and driven onto the third set of device pins during each clock cycle of the user-defined frequency.
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Specification