Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration

• US 7,157,350 B2
• Filed: 05/17/2004
• Issued: 01/02/2007
• Est. Priority Date: 05/17/2004
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Tze-Liang, Chen, Shih-Chang, Lin, Huan-Just, Yang, Ji-Yi, Chen, Chien-Hao
• Primary Examiner(s): Smith; Zandra V.
• Assistant Examiner(s): Duong; Khanh
• Application Number:
  US10/847,607
• Publication Number:
  US 20050253194A1
• Time in Patent Office: 960 Days
• Field of Search: 438/221, 438/296, 438/415, 438/424, 438/444, 438/445, 438/795
• US Class Current: 438/424
• CPC Class Codes: H01L 21/3247 for altering the shape, e.g. smoothing the surface
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.

Claims

1. A method of fabricating an SOI-like structure in a bulk silicon substrate, the structure being capable of acting as a device site, comprising:

forming a trench in the substrate, a wall of the trench defining a side of a device site, having an upper portion extending downwardly from a free surface of the substrate, and having a lower portion extending upwardly from the bottom of the trench;

forming a first oxide liner on the upper portion of to trench wail and exposing the lower portion of the trench wall; and

annealing the exposed lower trench wall portion in a deoxidizing ambient to effect self-organized migration of the silicon of the lower wall portion so as to form a void that extends at least partially under the device site and is in communication with the upper portion of the trench.

2. The method of claim 1, which further comprises filling the void and the trench with an insulative material.

3. The method of claim 1, which further comprises:

forming a second oxide liner on the wall of the void; and

filling the void and the trench with an insulative material.

4. The method of claim 1, wherein the annealing is carried out so that the wall of the void intersects a lower portion of the first oxide liner.

5. The method of claim 4, which further comprises forming a second oxide liner on the wall of the void so that the second oxide liner and the first oxide liner are contiguous.

6. The method of claim 5, which further comprises filling the trench and the void with an insulative material after the second oxide liner is formed.

7. The method of claim 1, wherein the annealing is carried out in a hydrogen-containing atmosphere, and, as the annealing is carried out, the void expands.

8. The method of claim 7, wherein the annealing is carried out at a temperature ranging from about 800°

C. to about 950°

C.

9. The method of claim 8, wherein the annealing is carried out until the wall of the expanding void intersects the lower portion of the first oxide liner.

10. The method of claim 9, which further comprises forming a second oxide liner on the wall of the void so that the second oxide liner and the first oxide liner are contiguous.

11. The method of claim 10, which further comprises filling the trench and the void with an insulative material after the second oxide liner is formed.

12. A method of fabricating an SOI-like structure in a bulk silicon substrate, the structure being capable of acting as a device site, comprising:

forming a trench in the substrate, opposed walls of the trench defining respective sides of neighboring device sites, each wall having an upper portion extending downwardly from a free surface of the substrate and a lower portion extending upwardly from the bottom of/the trench;

forming a first oxide liner on the upper portions of the trench walls and exposing the lower portions of the trench walls; and

annealing the exposed lower trench wall portions in a deoxidizing ambient to effect self-organized migration of the silicon of the lower wall portions so as to transform the lower wall portions into voids that extend at least partially under a respective device site and are in communication with the upper portions of the trench.

13. The method of claim 12, which further comprises filling the voids and the trench with an insulative material.

14. The method of claim 12, which further comprises:

forming a second oxide liner on the walls of the voids; and

filling the voids and the trench with an insulative material.

15. The method of claim 12, wherein the annealing is effected so that the wall of each void intersects the lower terminus of the oxide liner of the trench wall.

16. The method of claim 15, which further comprises forming a second oxide liner on the wall of each void so that the second oxide liner and the first oxide liner of the trench wall are contiguous.

17. The method of claim 16, which further comprises filling the trench and the voids with an insulative material after the second oxide liner is formed.

18. The method of claim 12, wherein the annealing is carried out in a hydrogen-containing atmosphere, and, as the annealing is carried out, the voids expand.

19. The method of claim 18, wherein the annealing is carried out at a temperature ranging from about 800°

C. to about 950°

C.

20. The method of claim 19, wherein the annealing is carried out until the wall of each void intersects the lower portion of the first oxide liner on the trench wall.

21. The method of claim 20, which further comprises forming a second oxide liner on the walls of the voids so that the second oxide liner and the first oxide liner on the trench wall are contiguous.

22. The method of claim 21, which further comprises filling the trench and the voids with an insulative material after the second oxide liner is formed.

23. A method of fabricating an SOI-like structure in a bulk silicon substrate, the structure being capable of acting as a device site, comprising:

forming two trenches in the substrate, the respective sides of a device site being defined by one wall of each trench, each side-defining wall having an upper portion extending downwardly from a free surface of the substrate and a lower portion extending upwardly from the bottom of its trench;

forming a first oxide liner on each side-defining trench wall and exposing the lower portions of the side-defining trench walls; and

annealing the exposed lower portion of each side-defining trench wall in a deoxidizing ambient to effect self-organized migration of the silicon of the lower side-defining wall portions so as to transform each lower side-defining trench wall portion into a void that extends under the device site and is in communication with its trench.

24. The method of claim 23, wherein as the annealing is carried out, the voids expand, and wherein the annealing is carried out until the voids approach a point of merger under the device site.

25. The method of claim 24, which further comprises filling the voids and the trenches with an insulative material.

26. The method of claim 24, which further comprises:

forming a second oxide liner on the walls of the voids; and

filling the voids and the trenches with an insulative material.

27. The method of claim 24, wherein the annealing is effected so that the wall of each void intersects the lower portion of the first oxide liner on the trench wall.

28. The method of claim 27, which further comprises forming a second oxide liner on the wall of each void so that the second oxide liner and the first oxide liner on the associated trench wall are contiguous.

29. The method of claim 28, which further comprises filling the trenches and the voids with an insulative material after the first oxide liner is formed on the wall of each void.

30. The method of claim 24, wherein the annealing is carried out in a hydrogen-containing atmosphere, and, as the annealing is carried out, the voids expand.

31. The method of claim 30, wherein the annealing is carried out at a temperature ranging from about 800°

C. to about 950°

C.

32. The method of claim 31, wherein the annealing is carried out until the wall of each void intersects the lower portion of the first oxide liner on the trench wall.

33. The method of claim 32, which further comprises forming a second oxide liner on the wall of each void so that the second oxide liner and the first oxide liner on the trench wall are contiguous.

34. The method of claim 33, which further comprises filling the trenches and the voids with an insulative material after the first oxide liner is formed on the walls of the voids.

35. The method of claim 23, wherein:

as the annealing is carried out, the voids expand; and

the annealing is carried out until the wall of each void intersects the lower portion of the first oxide liner on the trench wall, and the voids approach a point of merger under the device site.

36. The method of claim 35, which further comprises forming a second oxide liner on the walls of the voids.

37. The method of claim 36, wherein the formation of the second oxide liner consumes and substantially narrows the volume of silicon under the device site.

38. The method of claim 37, which further comprises filling the trenches and the voids with an insulative material after the second oxide liner is formed on the walls of the voids.

39. The method of claim 36, wherein the formation of the second oxide liner consumes and substantially eliminates silicon under the device site.

40. The method of claim 39, which further comprises filling the trenches and the voids with an insulative material after the second oxide liner is formed on the walls of the voids.

41. A method of fabricating an SOI-like structure in a bulk semiconductor substrate, comprising:

forming a trench in the substrate, a wall of the trench defining a side of a device site and having an upper portion extending downwardly from a free surface of the substrate and a lower portion extending upwardly from the bottom of the trench;

treating the lower trench wall portion to transform the lower trench wall portion into a void communicating with the upper portion of the trench and extending under the device site and

protecting the upper trench wall portion during the treating step;

wherein protecting the upper trench wall portion during the treating step includes lining the upper trench wall portion with an oxide layer while leaving the lower trench wall portion exposed.

42. A method of fabricating an SOI-like structure in a bulk semiconductor substrate, the structure being capable of acting as a semiconductor device site, the atoms of the substrate being capable of self-organized migration when the substrate is exposed to a heated deoxidizing atmosphere, comprising:

forming two trenches in the substrate, one wall of each trench defining respective sides of a device site, each side-defining wall having an upper portion extending downwardly from a free surface of the substrate and a lower portion extending upwardly from the bottom of the trench; and

annealing in a heated deoxidizing atmosphere and thereby effecting self-organized migration of the atoms in the respective lower wall portions to transform the respective lower wall portions into neighboring voids communicating with the upper portion of their respective trench and extending under the device site, while protecting the respective upper wall portions to minimize self-organized migration of atoms during the annealing step;

wherein while protecting the respective upper wall portions to minimize self-organized migration of atoms during the annealing step includes forming a first oxide liner on the trench wall, including the upper portion and the lower portion, and removing the first oxide liner from the lower portion of the trench wall while leaving the first oxide liner extant on the upper portion of the trench wall.