Peripheral device feature allowing processors to enter a low power state

  • US 7,159,766 B2
  • Filed: 01/20/2004
  • Issued: 01/09/2007
  • Est. Priority Date: 01/20/2004
  • Status: Active Grant
First Claim
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1. A system, comprising:

  • a processor;

    a host controller coupled to the processor; and

    a device coupled to the host controller;

    wherein the device is electrically disconnected from the host controller if the device is not in an active state; and

    wherein the device being electrically disconnected from the host controller causes an appearance to the host controller that the device is not coupled to the host controller; and

    wherein a sideband signal is used to signal the device to electrically reconnect after the device has been electrically disconnected.

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