Current-controlled CMOS logic family

• US 7,215,169 B2
• Filed: 03/21/2006
• Issued: 05/08/2007
• Est. Priority Date: 06/28/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Hairapetian, Armond
• Primary Examiner(s): Callahan; Timothy P.
• Assistant Examiner(s): Nguyen; Hai L.
• Application Number:
  US11/385,632
• Publication Number:
  US 20060176094A1
• Time in Patent Office: 413 Days
• Field of Search: 327/100, 327/210, 327/407, 327/415, 327/437, 326/62, 326/81
• US Class Current: 327/210
• CPC Class Codes: H03K 17/04 Modifications for accelerating switching
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/04163 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence
• CPC Class Codes: H03K 19/215 using field-effect transistors
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 3/356043 with synchronous operation
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/3562 of the master-slave type

Abstract

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C³MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C³MOS logic with low power conventional CMOS logic. The combined C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Claims

1. An apparatus, comprising:

a first circuit block, implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to receive and process a first signal thereby generating a second signal there from, wherein the first signal is a differential signal;

a second circuit block, implemented using conventional CMOS logic wherein substantially zero static current is dissipated, that is operable to receive and process a third signal thereby generating a fourth signal there from, wherein the second signal is a differential signal; and

a third circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to;

receive the second signal;

receive the fourth signal; and

process the second signal and the fourth signal thereby generating a fifth signal there from.

2. The apparatus of claim 1, wherein:

the fifth signal is a serialized signal that includes information contained within the second signal and the fourth signal.

3. The apparatus of claim 1, wherein:

the first signal has a first frequency;

the second signal has the first frequency; and

the fifth signal has a second frequency.

4. The apparatus of claim 1, wherein:

the first signal has a first frequency;

the second signal has the first frequency;

the fifth signal has a second frequency; and

the second frequency is greater than the first frequency.

5. The apparatus of claim 1, wherein:

the first signal has a first frequency;

the second signal has the first frequency;

the fifth signal has a second frequency; and

the second frequency is an integer multiple of the first frequency.

6. The apparatus of claim 1, further comprising:

a fourth circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to receive and process a sixth signal thereby generating the first signal and the third signal there from.

7. The apparatus of claim 6, wherein:

the first signal has a first frequency;

the second signal has the first frequency; and

the fifth signal has a second frequency; and

the sixth signal has the second frequency.

8. The apparatus of claim 1, wherein:

the first circuit block, the second circuit block, and the third circuit block are all implemented on a single silicon die.

9. An apparatus, comprising:

a first circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to receive and process a first signal thereby generating a second signal and a third signal there from;

a second circuit block, implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to receive and process the second signal thereby generating a fourth signal there from; and

a third circuit block, implemented using conventional CMOS logic wherein substantially zero static current is dissipated, that is operable to receive and process the third signal thereby generating a fifth signal there from.

10. The apparatus of claim 9, wherein:

the first circuit block deserializes the first signal thereby generating the second signal and the third signal there from such that the second signal includes first information contained within the first signal and the third signal includes second information contained within the first signal.

11. The apparatus of claim 9, wherein:

the first signal has a first frequency;

the second signal has a second frequency; and

the third signal has the second frequency.

12. The apparatus of claim 9, wherein:

the first signal has a first frequency;

the second signal has a second frequency;

the third signal has the second frequency; and

the first frequency is greater than the second frequency.

13. The apparatus of claim 9, wherein:

the first signal has a first frequency;

the second signal has a second frequency;

the third signal has the second frequency;

the fourth signal has the second frequency;

the fifth signal has the second frequency; and

the first frequency is greater than the second frequency.

14. The apparatus of claim 9, wherein:

the first circuit block, the second circuit block, and the third circuit block are all implemented on a single silicon die.

15. An apparatus, comprising:

a first circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to receive and process a first signal thereby generating a second signal and a third signal there from;

a second circuit block, implemented using conventional complementary metal-oxide semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to receive and process the second signal thereby generating a fourth signal there from;

a third circuit block, implemented using conventional CMOS logic wherein substantially zero static current is dissipated, that is operable to receive and process the third signal thereby generating a fifth signal there from.

a fourth circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to;

receive the fourth signal;

receive the fifth signal; and

process the fourth signal and the fifth signal thereby generating a sixth signal there from.

16. The apparatus of claim 15 wherein:

the first circuit block deserializes the first signal thereby generating the second signal and the third signal there from such that the second signal includes first information contained within the first signal and the third signal includes second information contained within the first signal.

17. The apparatus of claim 15, wherein:

the fourth circuit block serializes the fourth signal and the fifth signal thereby generating the sixth signal such that the sixth signal includes information contained within the fourth signal and the fifth signal.

18. The apparatus of claim 15, wherein:

the first signal has a first frequency;

the second signal has a second frequency;

the fourth signal has the second frequency; and

the sixth signal has the first frequency.

19. The apparatus of claim 15, wherein:

the first signal has a first frequency;

the second signal has a second frequency;

the third signal has the second frequency;

the fourth signal has the second frequency;

the fifth signal has the second frequency; and

the sixth signal has the first frequency.

20. The apparatus of claim 15, wherein:

the first circuit block, the second circuit block, the third circuit block, and the fourth circuit block are all implemented on a single silicon die.