Semiconductor device and manufacturing method thereof

• US 7,238,608 B2
• Filed: 07/25/2003
• Issued: 07/03/2007
• Est. Priority Date: 10/27/1999
• Status: Expired due to Term

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Anezaki, Toru, Ikemasu, Shinichiroh
• Primary Examiner(s): Smith; Matthew
• Assistant Examiner(s): Stark; Jarrett J.
• Application Number:
  US10/626,514
• Publication Number:
  US 20060197230A1
• Time in Patent Office: 1,439 Days
• Field of Search: 438253-254, 438396-397, 438/399, 438/401, 438/462, 438631-640, 438/673, 438/701, 438/975, 257/311, 257/797, 257/E21.018, 257/E21.507, 257/E21.577, 257/E21.649, 257/E21.658, 257/E27.088
• US Class Current: 438/637
• CPC Class Codes: G03F 9/7076 Mark details, e.g. phase grating mark, temporary mark
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A semiconductor device comprises a first insulating film formed over a semiconductor substrate, a second insulating film formed on the first insulating film, a contact plug made of a conductive material vertically penetrating the first and second insulating films and extending on the second insulating film, and a conductor film in contact with the upper surface of the contact plug and part of the second insulating film. This construction makes it possible to form minute via-holes in a mass-production line without increasing parasitic capacity, increasing the number of manufacturing steps, and generating defects.

Claims

1. A method of manufacturing a semiconductor device having a memory cell region and a peripheral region, comprising the steps of:

forming an alignment mark for positioning made of a conductive material, in said peripheral region;

forming a first insulating film so as to cover said alignment mark and extend to said memory cell region;

forming a second insulating film on said first insulating film;

forming a third insulating film on said second insulating film, said third insulating film having a low etching rate in relation to a first etchant for said first insulating film;

forming an opening portion so as to extend through said third and second insulating films up to said first insulating film;

forming a spacer on the side wall of said opening portion, said spacer having a low etching rate in relation to said first etchant for said first insulating film;

forming a first contact hole so as to extend through said first insulating film, using said third insulating film and said spacer as masks;

filling said opening portion and said first contact hole with a first conductive material to form a contact plug; and

selectively removing said third insulating film using a second etchant whose etching rate to said second insulating film is low.

2. A method according to claim 1, wherein said first, second, and third insulating films are transparent in relation to visible light.

3. A method according to claim 2, wherein said first insulating film is a silicon oxide film, said second insulating film is a silicon nitride film which grew through a low-pressure chemical vapor deposition process, and said third insulating film is a silicon nitride film which grew through a plasma chemical vapor deposition process.

4. A method according to claim 3, wherein said silicon nitride film which grew through said plasma chemical vapor deposition process, is removed with an aqueous solution of hydrofluoric acid, using, as an etching stopper, said silicon nitride film which grew through said low-pressure chemical vapor deposition process.

5. A method according to claim 3, wherein the thickness of said silicon nitride film which grew through said plasma chemical vapor deposition process, is eight times or less that of said silicon nitride film which grew through said low-pressure chemical vapor deposition process.

6. A method according to claim 1, further comprising, after the step of selectively removing said third insulating film, the steps of:

forming a fourth insulating film so as to cover the exposed surfaces of said contact plug and said spacer;

forming a second contact hole in said fourth insulating film so as to expose part of the surface of said contact plug and at least part of the side surface of said spacer;

forming a second conductive material on the side and bottom surfaces of said second contact hole;

selectively removing said fourth insulating film using an etchant whose etching rate to said second conductive material and said second insulating film is low.

7. A method according to claim 6, wherein said spacer is made of a conductive material and electrically connected to said second conductive material together with said contact plug.

8. A method according to claim 6, wherein said second conductive material is used as a storage node of DRAM.