Memory bus checking procedure

  • US 7,275,186 B2
  • Filed: 04/06/2006
  • Issued: 09/25/2007
  • Est. Priority Date: 07/02/2003
  • Status: Active Grant
First Claim
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1. A method for checking a data bus between a first electronic module and a second electronic module operatively connected to the first electronic module, said method comprising:

  • conveying from the first electronic module to the second electronic module a first bit pattern through the data bus;

    receiving in the first electronic module a second bit pattern from the second electronic module through the data bus;

    the second bit pattern contains at least a part of a complementary pattern of the first bit pattern;

    comparing the received second bit pattern to the first bit pattern for determining a usable bus width of the data bus based on a relationship between the first bit pattern and the complementary pattern of the first bit pattern.

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