Semiconductor chip and manufacturing method for the same, and semiconductor device

• US 7,282,444 B2
• Filed: 12/06/2004
• Issued: 10/16/2007
• Est. Priority Date: 12/04/2003
• Status: Active Grant

• Current Assignee: Kioxia Corporation, Sanyo Electric Company Limited (Panasonic Holdings Corporation), ROHM Co., Ltd.
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation), Renesas Technology Corporation (Renesas Electronics Corporation), ROHM Co., Ltd., Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takahashi, Kenji, Tanida, Kazumasa, Nemoto, Yoshihiko, Umemoto, Mitsuo
• Primary Examiner(s): Everhart; Caridad
• Application Number:
  US11/003,769
• Publication Number:
  US 20050151228A1
• Time in Patent Office: 1,044 Days
• Field of Search: 438/667, 438/589, 438/459, 257/698, 257/E21.597
• US Class Current: 438/667
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

The invention provides a semiconductor chip manufacturing method including the steps of: forming a concave portion extended in the thickness direction of a semiconductor substrate which has a front surface and a rear surface and has a function device formed on the front surface, from the front surface; forming an oxidation preventive film made of an inert first metal material by supplying the first metal material onto the inner wall surface of the concave portion; supplying a second metal material containing a metal which is oxidized more easily than the first metal material to the inside of the concave portion after the step of forming the oxidation preventive film; electrically connecting the second metal material supplied to the inside of the concave portion and the function device; and thinning the semiconductor substrate so that the thickness thereof becomes thinner than the depth of the concave portion by removing the semiconductor substrate from the rear surface while leaving the oxidation preventive film.

Claims

1. A semiconductor chip manufacturing method comprising the steps of:

providing a semiconductor substrate having a front surface and a rear surface, the front surface having a first portion and a second portion;

forming a function device on the second portion of the front surface;

forming a concave portion in the semiconductor substrate, the concave portion extending in a thickness direction of the semiconductor substrate from the first portion of the front surface;

forming an oxidation preventive film made of a first metal material by supplying the first metal material onto an inner wall surface of the concave portion;

supplying a second metal material containing a metal that is oxidized more easily than the first metal material into the concave portion after the step of forming the oxidation preventive film;

electrically connecting the second metal material supplied into the concave portion and the function device; and

thinning the semiconductor substrate, so that the thickness thereof becomes thinner than a depth of the concave portion, by removing the semiconductor substrate from the rear surface without removing the oxidation preventive film, the concave portion being formed into a through hole penetrating the semiconductor substrate in the thickness direction, and so that the second metal material disposed inside the concave portion is formed into both (i) a penetrating electrode that electrically connects the front surface and the rear surface and (ii) a rear side protruding electrode protruding from the rear surface,

wherein the step of supplying the second metal material into the concave portion and the step of electrically connecting the second metal material and the function device are simultaneously carried out.

2. A semiconductor chip manufacturing method according to claim 1, wherein the first metal material is selected from the group consisting of gold and palladium.

3. A semiconductor chip manufacturing method according to claim 1, further comprising a step of forming an insulating film on the inner wall surface of the concave portion before the step of forming the oxidation preventive film after the step of forming the concave portion.

4. A semiconductor chip manufacturing method according to claim 1, further comprising a step of forming a diffusion preventive film on the inner wall surface of the concave portion before the step of forming the oxidation preventive film after the step of forming the concave portion, the diffusion preventive film restraining diffusion of metal atoms from an inside of the through hole to the semiconductor substrate.

5. A semiconductor chip manufacturing method according to claim 1, further comprising a step of forming an intermetallic diffusion preventive film on the inner wall surface of the concave portion before the step of supplying the second metal material into the concave portion after the step of forming the oxidation preventive film, the intermetallic diffusion preventive film restraining diffusion of metal atoms between the oxidation preventive film and the second metal material.

6. The semiconductor chip manufacturing method according to claim 1, wherein:

the step of forming the oxidation preventive film further includes a step of supplying the first metal material onto the front surface, so that the oxidation preventive covers, without discontinuity, the inner wall surface of the concave portion and at least a portion of the function device formed on the second portion of the front surface; and

the oxidation preventive film electrically connects the second metal material to the function device.

7. A semiconductor chip manufacturing method according to claim 1, wherein:

the second metal material contains a low melting point metal material the solidus temperature of which is in a temperature range of 60°

C. or higher and 370°

C. or lower; and

the step of supplying the second metal material into the concave portion further includes a step of forming a low melting point metal layer by supplying the low melting point metal material to a bottom of the concave portion.

8. A semiconductor chip manufacturing method according to claim 7, wherein the step of forming the low melting point metal layer includes a step of supplying a low melting point metal paste containing a powder made of the low melting point metal material to the bottom of the concave portion.

9. A semiconductor chip manufacturing method comprising the steps of:

forming hole opened to one surface of a semiconductor substrate on which a function device is formed;

embedding a polymer inside the hole;

forming an interconnection layer electrically connected to the function device on an exposed surface of the polymer embedded inside the hole; and

forming a protruding electrode on the interconnection layer on the polymer.

10. A semiconductor chip manufacturing method according to claim 9, wherein the step of forming the interconnection layer includes a step of forming the interconnection layer so that the polymer is exposed between the edges of the hole and the interconnection layer.

11. A semiconductor chip manufacturing method according to claim 9, wherein

the step of forming the hole includes a step of forming concave portion as the hole,

the function device is formed on the one surface of the semiconductor substrate, and

the semiconductor chip manufacturing method further comprises the steps of:

forming a conductive film electrically connected to the function device by supplying a conductive material to the inner wall surface of the concave portion before the step of embedding the polymer into the concave portion after the step of forming the concave portion; and

thinning the semiconductor substrate so that the thickness thereof is reduced to be thinner than the depth of the concave portion by removing the semiconductor substrate from the other surface different from the one surface, the concave portion is formed into through hole penetrating the semiconductor substrate in the thickness direction, and the conductive film is disposed across the one surface side and the other surface side of the semiconductor substrate.

12. A semiconductor chip, comprising:

a semiconductor substrate having a front surface and a rear surface;

a function device formed on the front surface of the semiconductor substrate;

a penetrating electrode which is disposed inside a through hole penetrating the semiconductor substrate in a thickness direction by a side of the function device, and electrically connects the front surface of the semiconductor substrate and the rear surface of the semiconductor substrate;

an interconnection member electrically connecting the penetrating electrode to the function device, the interconnection member being made of the same material as the penetrating electrode;

a rear side protruding electrode which protrudes from the rear surface of the semiconductor substrate and has a side surface continued to a side surface of the penetrating electrode; and

an oxidation preventive film which covers the rear side protruding electrode, and is disposed between the semiconductor substrate and the penetrating electrode inside the through hole, and is made of an inert metal material.

13. A semiconductor chip according to claim 12, wherein the oxidation preventive film is made of metal selected from the group consisting of gold and palladium.

14. A semiconductor chip according to claim 12, further comprising an insulating film which is disposed between the oxidation preventive film and the semiconductor substrate inside the through hole.

15. A semiconductor chip according to claim 12, further comprising a diffusion preventive film which is disposed between the oxidation preventive film and the semiconductor substrate inside the through hole, and restrains diffusion of metal atoms from an inside of the through hole to the semiconductor substrate.

16. A semiconductor chip according to claim 12, further comprising an intermetallic diffusion preventive film which is disposed between the oxidation preventive film and the penetrating electrode inside the through hole, and restrains diffusion of metal atoms between the oxidation preventive film and the penetrating electrode.

17. A semiconductor chip according to claim 12, wherein at least a tip end side of the rear side protruding electrode is made of low melting point metal layer whose solidus temperature is in a temperature range of 60°

C. or higher and 370°

C. or lower.

18. The semiconductor chip according to claim 12, wherein the oxidation preventive film covers, without discontinuity, the rear side protruding electrode, the side surface of the penetrating electrode and at least a portion of the function device, and electrically connects the penetrating electrode to the function device.

19. A semiconductor chip comprising:

a semiconductor substrate with a function device formed thereon;

a polymer disposed so as to fill the inside of a hole opened to one surface of the semiconductor substrate;

an interconnection layer which is formed on the polymer embedded inside the hole and electrically connected to the function device; and

a protruding electrode provided on a portion positioned above the polymer of the interconnection layer.

20. A semiconductor chip according to claim 19, wherein the polymer is exposed between the edges of the hole and the interconnection layer.

21. A semiconductor chip comprising:

a semiconductor substrate with a function device formed thereon;

a polymer disposed inside a through hole penetrating the semiconductor substrate in the thickness direction;

an interconnection layer which is formed on the polymer disposed inside the through hole and electrically connected to the function device;

a protruding electrode provided on a portion positioned above the polymer of the interconnection layer; and

a conductive film which is disposed across one surface and the other surface of the semiconductor substrate inside the through hole and electrically connected to the function device.

22. A semiconductor device including a plurality of semiconductor chips stacked in the thickness direction, wherein

each semiconductor chip comprises:

a semiconductor substrate having a front surface and a rear surface;

a function device formed on the front surface of the semiconductor substrate;

a penetrating electrode which is electrically connected to the function device, disposed inside a through hole penetrating the semiconductor substrate in the thickness direction by the side of the function device, the penetrating electrode electrically connecting the front surface side and the rear surface side of the semiconductor substrate;

a rear side protruding electrode which protrudes from the rear surface of the semiconductor substrate and has a side surface continued to the side surface of the penetrating electrode; and

an oxidation preventive film which covers the rear side protruding electrode, and is disposed between the semiconductor substrate and the penetrating electrode inside the through hole and made of an inert metal material.

23. A semiconductor device including a plurality of semiconductor chips stacked in the thickness direction, wherein

each semiconductor chip comprises:

a semiconductor substrate with a function device formed thereon;

a polymer disposed so as to fill the inside of a hole opened to one surface of the semiconductor substrate;

an interconnection layer which is formed on the polymer embedded inside the hole and electrically connected to the function device; and

a protruding electrode provided on a portion positioned above the polymer of the interconnection layer.

24. A semiconductor device including a plurality of semiconductor chips stacked in the thickness direction, wherein

each semiconductor chip comprises:

a semiconductor substrate with a function device formed thereon;

a polymer disposed inside a through hole penetrating the semiconductor substrate in the thickness direction;

an interconnection layer which is formed on the polymer disposed inside the through hole and electrically connected to the function device;

a protruding electrode provided on a portion positioned above the polymer of the interconnection layer; and

a conductive film which is disposed across one surface and the other surface of the semiconductor substrate inside the through hole and is electrically connected to the function device.