Pattern forming method, mask manufacturing method, and LSI manufacturing method

• US 7,346,882 B2
• Filed: 07/30/2002
• Issued: 03/18/2008
• Est. Priority Date: 07/30/2001
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Abe, Takayuki
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): TAT, BINH C
• Application Number:
  US10/207,167
• Publication Number:
  US 20030026472A1
• Time in Patent Office: 2,058 Days
• Field of Search: 716/1, 716/2, 716 19- 21, 430/5, 430/30, 430/22
• US Class Current: 716/52
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging

Abstract

A pattern forming method includes the steps of checking a wide range size change characteristic for each device in a case of using a device group used for forming a pattern; dividing a design pattern size into a smaller area than a standard distance to which a predetermined size change is caused, when the pattern is formed on a sample by using the device group; acquiring correction information of the size of the pattern of each the small area by using the size change characteristic; and forming a desired pattern based on the acquired correction information.

Claims

1. A pattern forming method comprising:

checking a wide range size change characteristic for each device in a case of using a device group used for forming a pattern;

dividing a design pattern size into small areas each of which is smaller than a standard distance to which a predetermined size change is caused, when the pattern is formed on a sample by using the, device group;

acquiring correction information of the size of the pattern of each of the small areas by using the wide range size change characteristic; and

forming a desired pattern based on the acquired correction information, wherein, checking the wide range size change includes checking two correlations of a correlation between a position and a size change in a chip on a wafer or two or more chips and a correlation between a pattern characteristic and a size change.

2. The pattern forming method according to claim 1, wherein correction using the correction information is performed for each of the small areas.

3. The pattern forming method according to claim 1, wherein the predetermined size change is a size change in a wide range on the order of 1 cm order.

4. A manufacturing method of a mask comprising:

checking a correlation of a position and a size change and a correlations of a pattern characteristic and a size change on the mask in a case of using a device group used for manufacturing the mask;

correcting a design pattern size for small areas each of which is smaller than a standard distance to which a predetermined size change is caused by using data of each correlation, when the mask is manufactured by using the device group; and

forming a desired pattern on the mask based on the corrected design pattern size, wherein, checking the size change includes checking two correlations of a correlation between a position and a size change in a chip on a wafer or two or more chips and a correlation between a pattern characteristic and a size change.

5. A manufacturing method of an LSI comprising:

checking a correlation of a position and a size change and a correlation of a pattern characteristic and a size change in a chip on a wafer or a chip group in a case of using a device group used for a manufacturing process of the LSI;

correcting a design pattern size for smaller areas each of which is smaller than a standard distance to which a predetermined size change is caused by using data of the each correlation, when the LSI is manufactured by using the device group;

forming a desired pattern on a mask based on the corrected design pattern size; and

manufacturing the LSI by using the mask on which the desired pattern is formed, wherein, checking the size change includes checking two correlations of a correlation between a position and a size change in a chip on a wafer or two or more chips and a correlation between a pattern characteristic and a size change.

6. A manufacturing method of a mask comprising:

checking a correlation of a position and a size change and a correlations of a pattern characteristic and a size change on the mask in a case of using at least one of a plurality of devices used for manufacturing the mask;

correcting a design pattern size for smaller areas each of which is smaller than a standard distance to which a predetermined size change is caused by using data of the each correlation, when the mask is manufactured by using the each of the plurality of devices device; and

forming a desired pattern based on the corrected design pattern size, wherein, checking ihe size change includes checking two correlations of a correlation between a position and a size change in a chip on a wafer or two or more chips and a correlation between a panern characteristic and a size change.

7. A manufacturing method of an LSI comprising:

checking a first correlation of a position and a size change and a second correlation of a pattern characteristic and a size change in a chip on a wafer or a chip group in a case of using at least one of a plurality of devices used for a manufacturing process of the LSI;

correcting a design pattern size for smaller areas each of which is smaller than a standard distance to which a predetermined size change is caused by using data of the each of first and second correlations, when the LSI is manufactured by using the each of the plurality of devices;

forming a desired pattern on a mask based on the corrected design pattern size; and

manufacturing the LSI by using the mask on which the desired pattern is formed, wherein, checking the size change includes checking two correlations of a correlation between a position and a size change in a chip on a wafer or two or more chips and a correlation between a pattern characteristic and a size change.

8. The manufacturing method of an LSI according to claim 7, wherein the checking the correlations includes performing work of obtaining the first and the second correlations at substantially all processes, and obtaining the first and the second correlations in all processes from the first and second correlations in each process.