Method to engineer etch profiles in Si substrate for advanced semiconductor devices

• US 7,442,618 B2
• Filed: 07/16/2005
• Issued: 10/28/2008
• Est. Priority Date: 07/16/2005
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC), Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation, Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Chong, Yung Fu, Panda, Siddhartha, Greene, Brian Joseph, Rovedo, Nivo
• Primary Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US11/182,682
• Publication Number:
  US 20070020861A1
• Time in Patent Office: 1,200 Days
• Field of Search: 438/296, 438/424, 438/410, 438/435, 438/437, 257/E21.549
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.

Claims

1. A method of fabricating a trench comprising:

etching a substrate to form an upper portion of a trench, wherein the etching forms a passivation layer on sidewalls of the upper portion of the trench;

etching the substrate to form a rounded lower portion of the trench having a width greater than the upper portion, wherein the passivation layer protects the upper portion from being etched during etching to form the lower portion; and

wherein the upper portion and the rounded lower portion form an inverted keyhole trench.

2. The method of claim 1 wherein the upper portion comprises slanted sidewalls.

3. The method of claim 1 wherein the upper portion comprises slanted sidewalls having an angle from vertical between 1 and 60 degrees or 5 and 30 degrees.

4. The method of claim 1 which further includes filling the inverted keyhole trench with a material that insulates and creates compressive or tensile stress on the sidewalls of the inverted keyhole trench.

5. The method of claim 1 which farther includes forming a FET device having a channel region in said substrate;

and

filling the inverted keyhole trench with a material that insulates and creates compressive or tensile stress on the channel region.

6. The method of claim 1 further comprises forming a transistor having gate structure and a channel region in said substrate;

and

forming a plurality of trenches adjacent to the gate structure, wherein the trenches comprises upper portions and lower rounded portions with a width greater than the upper portions;

filling the trenches with a stress creating material to form stressor regions; and

forming source and drain regions at least partially in the stressor regions.

7. The method of claim 1 wherein the etching of the upper portion comprises an anisotropic etch and the etching of the lower portion comprises an isotropic etch.

8. The method of claim 7 wherein the anisotronic and isotropic etches comprise dry etches.

9. The method of claim 8 wherein the dry etches are performed insitu.

10. A method of fabricating a semiconductor device comprising:

providing a substrate;

etching an upper portion of a trench in the substrate, wherein a passivation layer is formed on sidewalls of upper portion of the trench during etching;

etching a lower portion of the trench while the passivation layer protects the upper portion, the lower portion comprises a rounded lower portion with a width greater than the upper portion;

wherein the upper and lower portions form an inverted keyhole trench; and

at least partially filling the inverted keyhole shaped trench with a material to create stress on the sidewalls of the inverted keyhole shaped trench to form a stress region.

11. The method of claim 10 wherein the upper portion comprises slanted sidewalls.

12. The method of claim 10 comprises filling the trench with a dielectric or semiconductor material.

13. The method of claim 10 wherein the etching of the upper portion comprises an anisotropic etch and the etching of the lower portion comprises an isotropic etch wherein the anisotropic etch forms a passivation layer on the first sidewalls and the passivation layer is etch resistant to the isotropic etch.

14. The method of claim 10 wherein the etching of the upper portion comprises an anisotropic etch and the etching of the lower portion comprises a dry isotropic etch.

15. The method of claim 10 wherein the etching of the upper portion comprises a dry anisotropic etch and the etching of the lower portion comprises a dry isotropic etch, wherein the anisotropic and isotropic etches are performed insitu.

16. A method for forming stressor regions comprising:

providing a substrate prepared with isolation regions defining an active region and a gate structure on the substrate in the active region;

forming trenches in source/drain regions adjacent to the isolation regions and the gate structure, wherein forming the trenches comprises

etching upper portions of the trenches in the source/drain regions of the substrate, wherein passivation layers are formed on sidewalls of the upper portions of the trenches during etching, and

etching lower portions of the trenches to form rounded lower portions with widths greater than the upper portions, the passivation layers protecting the upper portions during etching to form the lower portions; and

filling the trenches with a stress material to form stressor regions, wherein the stressor regions create stress in the substrate under the gate structure.

17. The method of claim 16 which further comprises forming source and drain regions at least partially in the stressor regions.

18. The method of claim 16 which further comprises forming source and drain regions at least partially in the stressor regions and in the substrate adjacent the gate structure, wherein the source and drain regions are formed using an implant process.

19. The method of claim 16 which further comprises forming source and drain regions at least partially in the stressor regions and in the substrate adjacent the gate structure, wherein the source and drain regions are formed by doping the stress material.

20. The method of claim 16 wherein the upper portion comprises slanted sidewalls.

21. The method of claim 16 wherein the etching of the upper portion comprises an anisotropic etch and the etching of the lower portion comprises a dry isotropic etch.