System and method for photolithography in semiconductor manufacturing

• US 7,501,227 B2
• Filed: 08/31/2005
• Issued: 03/10/2009
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Kuei Shun, Lin, Chin-Hsiang, Lu, David Ding-Chung
• Primary Examiner(s): Duda; Kathleen
• Application Number:
  US11/216,658
• Publication Number:
  US 20070048678A1
• Time in Patent Office: 1,287 Days
• Field of Search: 430/311, 430/312, 430/313, 430/394
• US Class Current: 430/312
• CPC Class Codes: G03F 7/203 comprising an imagewise exposure to electromagnetic radiation or corpuscular radiation
• CPC Class Codes: G03F 7/70341 Details of immersion lithography aspects, e.g. exposure media or control of immersion liquid supply chemical composition of immersion liquids G03F7/2041
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475

Abstract

A method for producing a pattern on a substrate includes providing at least one exposure of the pattern onto a layer of the substrate by a higher-precision lithography mechanism and providing at least one exposure of the pattern onto a layer of the substrate by a lower-precision lithography mechanism. The exposures can be done in either order, and additional exposures can be included. The higher-precision lithography mechanism can be immersion lithography and the lower-precision lithography mechanism can be dry lithography.

Claims

1. A method for producing a pattern on a substrate layer, the method comprising:

providing a pattern including a main feature and a dummy feature;

providing at least one first exposure onto the layer by a higher-precision lithography mechanism, wherein the first exposure produces the pattern on the layer; and

providing at least one second exposure onto the layer by a lower-precision lithography mechanism, wherein the second exposure removes the dummy feature from the pattern;

thereby producing the main feature on the layer.

2. The method of claim 1 wherein the higher-precision lithography mechanism is performed before the lower-precision lithography mechanism.

3. The method of claim 1 wherein the higher-precision lithography mechanism is performed after the lower-precision lithography mechanism.

4. The method of claim 1 wherein the higher-precision lithography mechanism is immersion lithography and the lower-precision lithography mechanism is dry lithography.

5. The method of claim 1, wherein the main feature is a contact hole and the dummy feature are dummy structures to provide a dense array of features on a mask used for the first exposure, wherein the dense array improves the depth of focus of the first exposure.

6. A method for photolithography in semiconductor manufacturing, comprising:

providing a first photoresist layer for a wafer;

providing a first mask for the wafer;

performing a first exposure on the wafer by immersion lithography, wherein the first exposure utilizes the first photoresist layer and the first mask, wherein the first exposure provides a pattern including a main feature; and

performing a second exposure on the wafer by dry lithography, wherein the second exposure utilizes the first photoresist layer, and wherein the second exposure changes an edge of the main feature.

7. The method of claim 6 wherein the second exposure is performed before the first exposure.

8. The method of claim 6 wherein a numerical aperture of the immersion lithography is greater than about 0.82.

9. The method of claim 6 wherein a fluid of the immersion lithography comprises a fluid having a PH value that is greater than 7.

10. The method of claim 6 wherein the immersion lithography comprises utilizing an electromagnetic source having a wavelength that is not greater than about 250 nm.

11. The method of claim 6 wherein the second exposure utilizes a second mask.

12. The method of claim 6 wherein the second exposure does not utilize a mask.

13. The method of claim 6 wherein the second exposure utilizes a beam source.

14. The method of claim 6 wherein the second exposure also utilizes a second photoresist layer.

15. The method of claim 6 wherein the second exposure is for an opening printing process using phase-shifting masks.

16. The method of claim 6 wherein a single etching process is applied to the wafer following both the first and second exposures.

17. The method of claim 6 wherein first and second etching processes are applied to the wafer following the first and second exposures, respectively.

18. The method of claim 6, wherein the changing the edge of the main feature includes rounding a corner of the main feature.

19. The method of claim 6, wherein the changing the edge of the main feature includes providing a line end of the main feature.

20. A method for double exposure photolithography in semiconductor manufacturing, comprising:

providing a first photoresist layer for a wafer;

providing a first mask for the wafer, wherein the first mask includes a pattern including an active feature and a dummy feature;

performing a first exposure to the wafer by immersion lithography wherein the first exposure utilizes the first photoresist layer and the first mask, and wherein a wavelength of light beams used for the immersion lithography is not greater than 193 nm, and wherein a numerical aperture of the immersion lithography is greater than about 0.75;

performing a first developing process of the first photoresist layer to form a first photoresist feature associated with the active feature and a second photoresist feature associated with the dummy feature;

performing a second exposure to the first photoresist layer of the wafer by dry lithography, wherein either a second mask or no mask is utilized for the second exposure; and

performing a second developing process of the first photoresist layer, wherein the second exposure and second developing process remove the second photoresist feature from the wafer.