Semiconductor device
First Claim
Patent Images
1. A semiconductor memory cell, comprising:
- at least one transistor, wherein the at least one transistor comprises;
a source region having a first doping profile;
a drain region having a second doping profile wherein the first doping profile is different from the second doping profile;
a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and
a gate spaced apart from, and capacitively coupled to, the body region;
wherein the memory cell stores at least one data state including (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell.
8 Assignments
0 Petitions
Accused Products
Abstract
A semiconductor integrated circuit device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.
146 Citations
20 Claims
-
1. A semiconductor memory cell, comprising:
-
at least one transistor, wherein the at least one transistor comprises; a source region having a first doping profile; a drain region having a second doping profile wherein the first doping profile is different from the second doping profile; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate spaced apart from, and capacitively coupled to, the body region; wherein the memory cell stores at least one data state including (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A semiconductor memory cell consisting essentially of a transistor, wherein the transistor comprises:
-
a source region having a first doping profile; a drain region having a second doping profile wherein the first doping profile is different from the second doping profile; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate spaced apart from, and capacitively coupled to, the body region; wherein the memory cell stores at least one data state including (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell. - View Dependent Claims (7, 8, 9, 10)
-
-
11. A semiconductor memory cell comprising at least one transistor, wherein the transistor comprises:
-
a source region having a first doping concentration; a drain region having a second doping concentration wherein the first doping concentration is different from the second doping concentration; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate spaced apart from, and capacitively coupled to, the body region; wherein the memory cell stores at least one data state including (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell. - View Dependent Claims (12, 13, 14)
-
-
15. A semiconductor memory cell comprising at least one transistor, wherein the transistor comprises:
-
a source region having a first geometry; a drain region having a second geometry wherein the first geometry is different from the second geometry; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate spaced apart from, and capacitively coupled to, the body region; wherein the memory cell stores at least one data state including (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification