Semiconductor module

• US 7,759,777 B2
• Filed: 04/16/2007
• Issued: 07/20/2010
• Est. Priority Date: 04/16/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Lai, Charlie Tan Tien, Schiess, Klaus, Otremba, Ralf, Schloegel, Xaver
• Primary Examiner(s): Pham; Hoai v
• Application Number:
  US11/735,762
• Publication Number:
  US 20080251903A1
• Time in Patent Office: 1,191 Days
• Field of Search: 257/668, 257/704, 257/735, 257/776, 257/784, 257/E23.06
• US Class Current: 257/668
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/142 Metallic substrates having insulating layers
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate

Abstract

A module having a semiconductor chip with a first contact element on a first main surface and a second contact element on a second main surface is disclosed. The semiconductor chip is arranged on a carrier. An insulating layer and a wiring layer cover the second main surface and the carrier.

Claims

1. A module comprising:

a semiconductor chip having a first contact element on a first main surface and a second contact element on a second main surface;

an electrically conductive carrier having a depression, wherein the semiconductor chip is arranged within the depression in such a way that the first main surface of the semiconductor chip faces the carrier, and wherein the first contact element is electrically conductively connected to the carrier; and

a first insulating layer and a wiring layer, which cover the second main surface of the semiconductor chip and the carrier.

2. The module of claim 1, comprising wherein the semiconductor chip is fixed to the carrier via an adhesion promoter and the adhesion promoter effects the electrically conductive connection.

3. The module of claim 1, comprising wherein an insulating material is arranged between a lateral face of the semiconductor chip and the carrier.

4. The module of claim 1, wherein the first insulating layer comprises a film.

5. The module of claim 4, comprising wherein the film is photopatternable.

6. The module of claim 1, comprising wherein the wiring layer connects the second contact element, to an external contact element and the external contact element has a larger contact area than the second contact element.

7. The module of claim 1, comprising wherein the semiconductor chip is a power semiconductor chip.