Reduced-step CMOS processes for low-cost radio frequency identification devices

• US 7,772,063 B2
• Filed: 08/11/2004
• Issued: 08/10/2010
• Est. Priority Date: 08/11/2004
• Status: Active Grant

• Current Assignee: Maurice Bailey
• Original Assignee: Identifi Technologies Incorporated
• Inventors: Novosel, David
• Primary Examiner(s): Stark, Jarrett J
• Application Number:
  US10/916,333
• Publication Number:
  US 20060033167A1
• Time in Patent Office: 2,190 Days
• Field of Search: 438/199, 438/174, 438/217, 257/E21.443
• US Class Current: 438/217
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects

Abstract

Reduced-step CMOS processes for low-cost integrated circuits (ICs) and, more particularly, low-cost radio frequency identification (RFID) devices are disclosed. The CMOS processes disclosed provide sufficient device performance and reliability while reducing the number and complexity of required process steps, thereby reducing the cost for manufacturing ICs. By recognizing the particular needs for low-cost integrated circuits such as RFID devices (for example, reduced needs for performance, power and longevity) and by identifying a reduced set of CMOS process steps, an advantageous solution is achieved for producing low-cost integrated circuits and low-cost RFID devices.

Claims

1. A method for CMOS processing of low-cost radio frequency identification (RFID) tag integrated circuits, comprising:

forming first-type well regions within a second-type semiconductor substrate;

creating second-type MOS transistors within the first-type well regions and first-type MOS transistors within the substrate without utilizing a lightly doped drain (LDD) process;

adjusting, separately from the forming and creating steps, threshold voltages for the first-type MOS transistors with a threshold voltage adjust implant processing step directed to the channel of the first-type MOS transistors, and allowing the channels of the second-type MOS transistors to be subjected to the threshold voltage adjust implant processing step as well, thereby allowing threshold voltages for the second-type MOS transistors to also be adjusted by the threshold voltage adjust implant processing step;

providing interconnect circuitry utilizing polysilicon layers without utilizing a silicide and utilizing two or fewer metal interconnect layers; and

fabricating an integrated radio frequency identification (RFID) tag integrated circuit utilizing the forming, creating, adjusting, and providing steps, the RFID tag integrated circuit including circuitry configured to communicate stored information to an RFID reader;

wherein the CMOS process has a minimum device geometry of 1.0 microns or less.

2. The method of claim 1, wherein the first-type is N-type, the second-type is P-type, the first-type MOS transistors are NMOS transistors, and the second-type MOS transistors are PMOS transistors.

3. The method of claim 1, wherein the first-type is P-type, the second-type is N-type, the first-type MOS transistors are PMOS transistors, and the second-type MOS transistors are NMOS transistors.

4. The method of claim 1, wherein the CMOS process has a minimum device geometry of 0.5 microns or less.

5. The method of claim 1, wherein the providing interconnect circuitry step comprises providing interconnections without utilizing metal plugs.

6. The method of claim 1, wherein the providing interconnect circuitry step is carried out without performing a chemical mechanical polishing (CMP) processing step.

7. The method of claim 1, wherein the first-type MOS and the second-type MOS transistors are not separated by a field implant.

8. The method of claim 1, further comprising forming embedded memory within the RFID tag.

9. The method of claim 8, wherein the embedded memory comprises non-volatile memory.

10. The method of claim 1, further comprising integrating an antenna with the integrated RFID tag.

11. The method of claim 1, wherein the fabrication utilizes a CMOS process with 9 or fewer masks.

12. The method of claim 11, wherein the process steps consists essentially of an N-well definition step, an active area definition step, a polysilicon patterning step, a source/drain implantation step, a contact definition step, a metal one patterning step, a via definition step, and a metal two patterning step.

13. The method of claim 11, wherein the process steps consists essentially of an N-well definition step, an active area definition step, a polysilicon patterning step, a source/drain implantation step, a contact definition step, a metal one patterning step, a via definition step, a metal two patterning step, and a passivation step.

14. The method of claim 1, wherein the RFID tag does not include electrostatic discharge (ESD) protection circuitry.

15. The method of claim 1, further comprising utilizing a starting wafer having a substrate lacking a lightly doped epitaxial (EPI) layer.

16. The method of claim 1, wherein the first-type MOS and the second-type MOS transistors are not separated by a field implant;

wherein the providing interconnect circuitry step is carried out without performing a chemical mechanical polishing (CMP) processing step;

wherein the RFID tag does not include electrostatic discharge (ESD) protection circuitry; and

wherein a starting wafer having a substrate lacking a lightly doped epitaxial (EPI) layer is utilized.

17. The method of claim 1, further comprising providing interconnect circuitry without utilizing a salicide process.

18. The method of claim 1, wherein the providing interconnect circuitry step comprises providing interconnect circuitry utilizing at least one metal interconnect layer.

26. The method of claim 11, wherein the fabrication utilizes a CMOS process with at least seven masks.

19. A method for CMOS processing of low-cost radio frequency identification (RFID) tag integrated circuits, comprising:

forming first-type well regions within a second-type semiconductor substrate;

creating second-type MOS transistors within the first-type well regions and first type MOS transistors within the substrate;

adjusting, separately from the forming and creating steps, threshold voltages for the first-type MOS transistors with a threshold voltage adjust implant processing step directed to the channel of the first-type MOS transistors, and allowing the channels of the second-type MOS transistors to be subjected to the threshold voltage adjust implant processing step as well, thereby allowing threshold voltages for the second-type MOS transistors to also be adjusted by the threshold voltage adjust implant processing step;

providing interconnect circuitry utilizing polysilicon layers and fabricating an integrated radio frequency identification (RFID) tag integrated circuit utilizing the forming, creating, adjusting, and providing steps, the RFID tag integrated circuit including circuitry configured to communicate stored information to an RFID reader;

wherein the CMOS process has a minimum device geometry of 1.0 microns or less; and

wherein the method further comprises one or more of the following process features;

creating the first-type MOS and the second-type MOS transistors such that they are not separated by a field implant;

providing the interconnect circuitry without performing a chemical mechanical polishing (CMP) processing step;

providing the interconnect circuitry without utilizing metal plugs;

providing a resulting integrated circuit that does not include electrostatic discharge (ESD) protection circuitry; and

utilizing a starting wafer having a substrate lacking a lightly doped epitaxial (EPI) layer.

20. The method of claim 19, wherein the first-type is N-type, the second-type is P-type, the first-type MOS transistors are NMOS transistors, and the second-type MOS transistors are PMOS transistors.

21. The method of claim 19, wherein the first-type is P-type, the second-type is N-type, the first-type MOS transistors are PMOS transistors, and the second-type MOS transistors are NMOS transistors.

22. The method of claim 19, wherein the CMOS process has a minimum device geometry of 0.5 microns or less.

23. The method of claim 19, further comprising providing interconnect circuitry without utilizing a salicide process.

24. The method of claim 19, wherein the step of creating includes creating second-type MOS transistors within the first-type well regions and first-type MOS transistors within the substrate without utilizing a lightly doped drain (LDD) process.

25. The method of claim 19, wherein the step of providing includes interconnect circuitry utilizing polysilicon layers without utilizing a silicide and utilizing two or fewer metal interconnect layers.