Dual stress memory technique method and related structure

• US 7,785,950 B2
• Filed: 11/10/2005
• Issued: 08/31/2010
• Est. Priority Date: 11/10/2005
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc., Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC), Samsung Electronics Co. Ltd.
• Original Assignee: International Business Machines Corporation, Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC), Samsung Electronics Co. Ltd.
• Inventors: Kim, Jun Jung, Luo, Zhijiong, Fang, Sunfei, Teh, Young Way, Rovedo, Nivo, Ng, Hung Y.
• Primary Examiner(s): Lee; Hsien-ming
• Assistant Examiner(s): PARENDO, KEVIN A
• Application Number:
  US11/164,114
• Publication Number:
  US 20070105299A1
• Time in Patent Office: 1,755 Days
• Field of Search: 438/199, 438/791, 257/E21.632
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Abstract

A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

Claims

1. A method of providing a dual stress memory technique in a semiconductor device including an nFET and a pFET, the method comprising:

forming a first stress layer over the nFET and the pFET, wherein the first stress layer is an intrinsically compressive stressed layer

forming an etch stop layer over the first stress layer;

removing the first stress layer and the etch stop layer over the nFET

forming a second stress layer over a remaining portion of the first stress layer and the nFET, wherein the second stress layer is a tensilely stressed silicon nitride layer;

annealing to memorize stress in the nFET and the pFET, wherein the remaining portion of the first stress layer remains over the pFET during the annealing, and the second stress layer remains over both the nFET and the pFET during the annealing; and

;

removing the first and second stress layers and the etch stop layer in their entirety, wherein the memorized stress is retained in the nFET and the pFET after the annealing and the removing of the first and second stress layers.

2. The method of claim 1, wherein the compressive stress silicon nitride includes a high density plasma (HDP) silicon nitride.

3. The method of claim 1, further comprising the step of depositing an additional etch stop layer prior to the first stress layer forming step.

4. The method of claim 1, wherein the compressive stress silicon nitride has a magnitude of stress of no less than 100 MPa after the annealing.

5. The method of claim 1, wherein the annealing step includes using a temperature of no less than approximately 400°

C. and no greater than approximately 1200°

C.

6. The method of claim 1, wherein each stress layer includes silicon nitride.

7. The method of claim 1, wherein the etch stop layer includes silicon dioxide.

8. A method of providing a dual stress memory technique for a semiconductor device including an nFET and a pFET, the method comprising:

forming a tensile stress layer over only the nFET and forming a compressive stress layer over the pFET and the tensile stress layer overlying the nFET, wherein the compressive stress layer includes silicon nitride;

annealing to memorize stress in the nFET and the pFET, wherein the tensile stress layer remains over only the nFET and the compressive stress layer remains over the pFET and the tensile stress layer overlying the nFET during the annealing; and

removing the compressive and tensile stress layers in their entirety, wherein the memorized stress is retained in the nFET and the pFET after the annealing and the removing of the compressive and tensile stress layers.

9. The method of claim 8, wherein the compressive stress layer forming step includes performing a high density plasma (HDP) deposition of the silicon nitride using the following conditions:

approximately 50 mTorr of pressure, approximately 200 standard cubic centimeters (sccm) argon (Ar), approximately 100 sccm of silane (SiH₄), approximately 300 sccm of nitrogen (N₂), approximately 0-1500 W of radio frequency (RF) bias power and approximately 2000 W-4500 W of RF source power.

10. The method of claim 8, wherein the annealing step includes using a temperature of no less than approximately 400°

C. and no greater than approximately 1200 °

C.

11. The method of claim 8, wherein the tensile stress layer includes silicon nitride.

12. The method of claim 8, wherein the forming step includes:

forming the tensile stress layer over the nFET and the pFET;

forming an etch stop layer over the tensile stress layer;

removing the tensile stress layer and the etch stop layer over the pFET; and

forming the compressive stress layer over a remaining portion of the tensile stress layer and the pFET.

13. The method of claim 12, wherein the etch stop layer includes silicon dioxide.