Semiconductor chip comprising a metal coating structure and associated production method

• US 7,880,300 B2
• Filed: 03/28/2007
• Issued: 02/01/2011
• Est. Priority Date: 09/28/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Haimerl, Alfred, Kessler, Angela, Schober, Wolfgang, Bauer, Michael, Mahler, Joachim
• Primary Examiner(s): Loke; Steven
• Assistant Examiner(s): Thomas; Kimberly M
• Application Number:
  US11/692,530
• Publication Number:
  US 20070228567A1
• Time in Patent Office: 1,406 Days
• Field of Search: 257/751, 257/758, 257/737, 257/E23.024, 257/E23.162, 257/739
• US Class Current: 257/739
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05017 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05557 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05562 On the entire exposed surface of the internal layer
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/48764 Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 23/3142 Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor chip (1) has a metal coating structure (2) which has on an active upper side (3) of the semiconductor chip (1) at least one lower metal layer (8) with copper or copper alloy, on which a central metal layer (9) with nickel is arranged. The metal coating structure (2) is terminated by an upper metal layer (10) of palladium and/or a precious metal. The central metal layer (9) with nickel and/or nickel phosphide has a rough interface (11) with respect to the plastic package molding compound surrounding the metal coating structure (2).

Claims

1. A semiconductor device comprising a semiconductor chip, the semiconductor chip comprising:

a bonding wire; and

a metal coating structure on an active upper side of the semiconductor chip, the metal coating structure comprising;

precious-metal-containing bonding areas on the upper side of the semiconductor chip, and

a plurality of metal layers arranged one on top of the other and comprising;

a copper-containing lower metal layer forming interconnects and contact terminal areas,

a central metal layer comprising at least one of nickel and nickel phosphide, covering the lower metal layer, and

an upper metal layer comprising a precious metal, covering at least the bonding areas and, the bonding wire being attached to the upper metal layer, the upper metal layer having a total thickness d_o such that 0.1 μ

m≦

d_o≦

1.0 μ

m,

wherein the central metal layer has a rough interface with respect to the upper metal layer such that an average roughness height t_m of the central metal layer is 0.05 μ

m≦

t_m≦

1.00 μ

m.

2. The semiconductor device according to claim 1, wherein a roughness of the interface of the central metal layer is formed galvanically in a front-end process by variation of current densities during deposition.

3. The semiconductor device according to claim 1, wherein a roughness of the interface of the central metal layer is such that there is great adhesiveness with respect to the plastic package molding compound, and the roughness of the interface of the central metal layer is further such that a bondability of the bonding areas is not impaired.

4. The semiconductor device according to claim 1, wherein a thickness d_u of the lower copper-containing metal layer of the coating structure is 2 μ

m≦

d_u≦

50 μ

m.

5. The semiconductor device according to claim 1, wherein a diffusion-inhibiting metal layer comprising at least one of tungsten and titanium is arranged between the copper-containing metal layer of the contact terminal areas and the contact areas of the semiconductor chip, which are in connection with the electrodes of semiconductor elements of the semiconductor chip.

6. The semiconductor device according to claim 1, wherein a metal layer comprising at least one of tungsten and titanium is arranged as a diffusion barrier between the copper-containing metal layer of the interconnects and the passivation layers of the upper side of the semiconductor chip.

7. The semiconductor device according to claim 1, wherein cross sections of the interconnects of the metal coating structure have such dimensions that the interconnects are capable of carrying source or emitter currents of power semiconductor chips.

8. The semiconductor device according to claim 1, wherein the metal coating structure covers a proportion of a surface area Δ

F of the active upper side of the semiconductor chip, with Δ

F 50%.

9. The semiconductor device according to claim 1, wherein the semiconductor device is a power device.

15. The semiconductor device of according to claim 1, wherein the upper metal layer covers only the bonding areas, and wherein the central metal layer further has a rough interface with respect to a plastic package molding compound surrounding the metal coating structure.

17. The semiconductor device of claim 1, wherein the upper metal layer has an upper surface that is rough, the bonding wire being connected to the rough upper surface of the upper metal layer.

10. A power semiconductor module comprising a semiconductor chip, the semiconductor chip comprising:

a bonding wire; and

a metal coating structure on an active upper side of the semiconductor chip, the metal coating structure comprising;

precious-metal-containing bonding areas on the upper side of the semiconductor chip, and

a plurality of metal layers arranged one on top of the other and comprising;

a copper-containing lower metal layer forming interconnects and contact terminal areas,

a central metal layer comprising at least one of nickel and nickel phosphide, covering the lower metal layer, and

an upper metal layer comprising a precious metal, covering at least the bonding areas, the bonding wire being attached to the upper metal layer, the upper metal layer having a total thickness d_o such that 0.1 μ

m≦

d_o≦

1.0 μ

m,

wherein the central metal layer has a rough interface with respect to the upper metal layer such that an average roughness height t_m of the central metal layer is 0.05 μ

m≦

t_m≦

1.00 μ

m.

18. The power semiconductor module of claim 10, wherein the upper metal layer has an upper surface that is rough, the bonding wire being connected to the rough upper surface of the upper metal layer.

11. A semiconductor chip comprising a metal coating structure on an active upper side of the semiconductor chip, the metal coating structure comprising:

precious-metal-containing bonding areas on the active upper side;

a plurality of metal layers arranged one on top of the other and comprising;

a copper-containing lower metal layer forming interconnects and contact terminal areas,

a central metal layer, comprising at least one of nickel and nickel phosphide, covering the lower metal layer, and

an upper metal layer comprising palladium, covering at least the bonding areas, the upper metal layer having a total thickness d_o such that 0.1 μ

m≦

d_o≦

1.0 μ

m,

wherein the central metal layer has a rough interface with respect to the upper metal layer such that an average roughness height t_m of the central metal layer is 0.05 μ

m≦

t_m≦

1.00 μ

m; and

a bonding wire attached to the upper metal layer.

12. The semiconductor chip according to claim 11, wherein a roughness of the interface of the central metal layer is formed galvanically in a front-end process by variation of current densities during deposition.

13. The semiconductor chip according to claim 11, wherein a roughness of the interface of the central metal layer is such that there is great adhesiveness with respect to the plastic package molding compound, and the roughness of the interface of the central metal layer is further such that a bondability of the bonding areas is not impaired.

14. The semiconductor chip according to claim 11, wherein a thickness d_u of the lower copper-containing metal layer of the coating structure is 2 μ

m≦

d_u≦

50 μ

m.

16. The semiconductor chip according to claim 11, wherein the upper metal layer covers only the bonding areas, and wherein the central metal layer further has a rough interface with respect to a plastic package molding compound surrounding the metal coating structure.

19. The semiconductor chip of claim 11, wherein the upper metal layer has an upper surface that is rough, the bonding wire being connected to the rough upper surface of the upper metal layer.

20. A semiconductor device comprising a semiconductor chip, the semiconductor chip comprising a metal coating structure on an active upper side of the semiconductor chip, the metal coating structure comprising:

precious-metal-containing bonding areas on the active upper side;

a plurality of metal layers arranged one on top of the other and comprising;

a copper-containing lower metal layer forming interconnects and contact terminal areas,

a central metal layer, comprising at least one of nickel and nickel phosphide, covering the lower metal layer, and

an upper metal layer comprising palladium, covering at least the bonding areas, the upper metal layer having a total thickness d_o such that 0.1 μ

m≦

d_o≦

1.0 μ

m,

wherein the central metal layer has a rough interface with respect to the upper metal layer such that an average roughness height t_m of the central metal layer is 0.05 μ

m≦

t_m≦

1.00 μ

m; and

a bonding wire attached to the upper metal layer.

21. The semiconductor device of claim 20, wherein the upper metal layer has an upper surface that is rough, the bonding wire being connected to the rough upper surface of the upper metal layer.

22. A power semiconductor module comprising a semiconductor chip, the semiconductor chip comprising a metal coating structure on an active upper side of the semiconductor chip, the metal coating structure comprising:

precious-metal-containing bonding areas on the active upper side;

a plurality of metal layers arranged one on top of the other and comprising;

a copper-containing lower metal layer forming interconnects and contact terminal areas,

a central metal layer, comprising at least one of nickel and nickel phosphide, covering the lower metal layer, and

an upper metal layer comprising palladium, covering at least the bonding areas, the upper metal layer having a total thickness d_o such that 0.1 μ

m≦

d_o≦

1.0 μ

m,

wherein the central metal layer has a rough interface with respect to the upper metal layer such that an average roughness height t_m of the central metal layer is 0.05 μ

m≦

t_m≦

1.00 μ

m; and

a bonding wire attached to the upper metal layer.

23. The power semiconductor module of claim 22, wherein the upper metal layer has an upper surface that is rough, the bonding wire being connected to the rough upper surface of the upper metal layer.