FPGA and method and system for configuring and debugging a FPGA
First Claim
1. A Field Programmable Gate Array including a logic unit under test, the Field Programmable Gate Array comprising:
- a probe signal selecting unit configured to select at least one probe point from a plurality of probe points in said logic unit under test and obtain a probe signal at said probe point;
a high speed serial transceiver configured to convert said probe signal into a high speed serial signal and transmit said high speed serial signal to outside the Field Programmable Gate Array, wherein said high speed serial transceiver also receives a stimulation signal;
a stimulation signal selecting unit configured to select a stimulation signal received by said high speed serial transceiver and apply it to said logic unit under test; and
a stimulation signal transforming unit configured to transform said stimulation signal into a signal that matches said stimulation signal selecting unit when said stimulation signal received by said high speed serial transceiver does not match said stimulation signal selecting unit.
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Abstract
The present invention provides a Field Programmable Gate Array (FPGA), a system for debugging a Field Programmable Gate Array, a method for debugging a Field Programmable Gate Array, a FPGA configuration data product and a method and system for configuring a FPGA. According to one aspect of the invention, there is provided a Field Programmable Gate Array (FPGA) having a logic unit under test and comprising: a probe signal selecting unit configured to select at least one probe point from a plurality of probe points in said logic unit under test, and obtain a probe signal at said probe point; and a high speed serial transceiver configured to convert said probe signal into a high speed serial signal and transmit it to outside.
21 Citations
12 Claims
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1. A Field Programmable Gate Array including a logic unit under test, the Field Programmable Gate Array comprising:
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a probe signal selecting unit configured to select at least one probe point from a plurality of probe points in said logic unit under test and obtain a probe signal at said probe point; a high speed serial transceiver configured to convert said probe signal into a high speed serial signal and transmit said high speed serial signal to outside the Field Programmable Gate Array, wherein said high speed serial transceiver also receives a stimulation signal; a stimulation signal selecting unit configured to select a stimulation signal received by said high speed serial transceiver and apply it to said logic unit under test; and a stimulation signal transforming unit configured to transform said stimulation signal into a signal that matches said stimulation signal selecting unit when said stimulation signal received by said high speed serial transceiver does not match said stimulation signal selecting unit. - View Dependent Claims (2, 3, 4, 5)
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6. A system for debugging Field Programmable Gate Arrays, the system comprising:
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a Field Programmable Gate Array including; a) a probe signal selecting unit configured to select at least one probe point from a plurality of probe points in said logic unit under test and obtain a probe signal at said probe point; and b) a high speed serial transceiver configured to convert said probe signal into a high speed serial signal and transmit said high speed serial signal to outside the Field Programmable Gate Array; c) a stimulation signal selecting unit configured to select a stimulation signal received by said high speed serial transceiver and apply it to said logic unit under test; and d) a stimulation signal transforming unit configured to transform said stimulation signal into a signal that matches said stimulation signal selecting unit when said stimulation signal received by said high speed serial transceiver does not match said stimulation signal selecting unit; an analyzing means configured to receive and analyze a signal sent by said high speed serial transceiver;
wherein said analyzing means further sends a stimulation signal to said high speed serial transceiver. - View Dependent Claims (7)
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8. A method for debugging a Field Programmable Gate Array having a logic unit under test, the method comprising:
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probing a probe signal of at least one probe point in said logic unit under test; converting said probe signal into a high speed serial signal and sending it to an external analyzing means; analyzing said signal; inputting a stimulation signal into said Field Programmable Gate Array in a form of a high speed serial signal; converting said high speed serial stimulation signal into a low speed parallel stimulation signal; and applying said stimulation signal to said logic unit under test. - View Dependent Claims (9)
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10. A computer program embodied in non-transitory computer readable memory, the computer program comprising:
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a probe signal selecting module configured to select at least one probe point from a plurality of probe points in a logic unit under test of a Field Programmable Gate Array, and obtain a probe signal at said probe point; a configuration module for enabling a high speed serial transceiver to convert said probe signal into a high speed serial signal and transmit it to outside the Field Programmable Gate Array, wherein said high speed serial transceiver is configured to also receive a stimulation signal; and a stimulation signal selecting module configured to select a stimulation signal received by said high speed serial transceiver and apply it to said logic unit under test; a stimulation signal transforming unit configured to transform said stimulation signal into a signal that matches said stimulation signal selecting unit when said stimulation signal received by said high speed serial transceiver does not match said stimulation signal selecting unit. - View Dependent Claims (11)
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12. A system for configuring a Field Programmable Gate Array, comprising loading configuration data into means in the Field Programmable Gate Array to enable the Field Programmable Gate Array to have following functional modules:
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a probe signal selecting unit configured to select at least one probe point from a plurality of probe points in a logic unit under test of said Field Programmable Gate Array, and obtain a probe signal at said probe point; a high speed serial transceiver configured to convert said probe signal into a high speed serial signal and transmit it to outside, wherein said high speed serial transceiver also receives a stimulation signal; a stimulation signal selecting unit configured to select a stimulation signal received by said high speed serial transceiver or a signal of other signal sources and apply it to said logic unit under test; and a stimulation signal transforming unit configured to transform said stimulation signal into a signal that matches said stimulation signal selecting unit when said stimulation signal received by said high speed serial transceiver does not match said stimulation signal selecting unit.
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Specification