Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material
First Claim
1. A method of forming an integrated MIM capacitor, comprising the steps of:
- providing a semiconductor substrate having a top surface;
forming a lower capacitor plate and a High K (HiK) dielectric layer (160) consisting of a material selected from the group consisting of Ta2O5, BaTiO3, HfO2, ZrO2, and Al2O3;
by the step comprising;
(i) forming a doped well (35) in said surface of said semiconductor substrate;
(a) then forming a silicide region (141B) in said surface of said doped well (35) followed by forming said High K (HiK) dielectric layer (160/40) on said surface of said silicide region (141B);
or(b) then forming said HiK dielectric layer (160) on said surface of said doped well (35);
or(ii) forming a Shallow Trench Isolation (STI) region (33) in said semiconductor substrate below said surface of said semiconductor substrate followed by forming a conductor layer (38P) overlying said STI region (33), andthen followed by forming said HiK dielectric layer (40) over said conductor layer (38P); and
then forming a second capacitor plate 142 over said HiK dielectric layer (40) above said lower capacitor plate.
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Accused Products
Abstract
A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers.
20 Citations
19 Claims
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1. A method of forming an integrated MIM capacitor, comprising the steps of:
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providing a semiconductor substrate having a top surface; forming a lower capacitor plate and a High K (HiK) dielectric layer (160) consisting of a material selected from the group consisting of Ta2O5, BaTiO3, HfO2, ZrO2, and Al2O3;
by the step comprising;(i) forming a doped well (35) in said surface of said semiconductor substrate; (a) then forming a silicide region (141B) in said surface of said doped well (35) followed by forming said High K (HiK) dielectric layer (160/40) on said surface of said silicide region (141B);
or(b) then forming said HiK dielectric layer (160) on said surface of said doped well (35);
or(ii) forming a Shallow Trench Isolation (STI) region (33) in said semiconductor substrate below said surface of said semiconductor substrate followed by forming a conductor layer (38P) overlying said STI region (33), and then followed by forming said HiK dielectric layer (40) over said conductor layer (38P); and then forming a second capacitor plate 142 over said HiK dielectric layer (40) above said lower capacitor plate. - View Dependent Claims (2)
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3. A method of forming an integrated Metal Insulator-Metal (MIM) capacitor on a semiconductor substrate comprising:
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forming a base comprising a semiconductor substrate having a top surface and including regions formed in said surface having exterior surfaces coplanar with said semiconductor substrate selected from the group comprising a doped P/N well and a Shallow Trench Isolation (STI) region; forming a lower capacitor plate selected from the group comprising a silicide electrode layer formed in said top surface of said doped P/N well, and a lower electrode formed on top of said STI region in said semiconductor substrate; forming a first capacitor High K (HiK) dielectric layer on said lower capacitor plate, and forming a second capacitor plate layer patterned into a second capacitor plate on said HiK dielectric layer above said lower capacitor plate. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification