Method for forming shielded gate field effect transistor using spacers

• US 7,935,577 B2
• Filed: 12/29/2008
• Issued: 05/03/2011
• Est. Priority Date: 06/29/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kraft, Nathan Lawrence, Grebs, Thomas E., Ridley, Rodney
• Primary Examiner(s): Garber; Charles D
• Assistant Examiner(s): Ahmadi; Mohsen
• Application Number:
  US12/344,859
• Publication Number:
  US 20090111231A1
• Time in Patent Office: 855 Days
• Field of Search: 257/E21.37, 257/E21.384, 257/E21.4
• US Class Current: 438/142
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. Dielectric spacers are formed along the upper trench sidewalls. After forming the dielectric spacers, an inter-electrode dielectric (IED) is formed in the trench over the shield electrode. After forming the IED, the dielectric spacers are removed.

Claims

1. A method for forming a field effect transistor comprising:

forming a trench in a semiconductor region;

forming a dielectric layer lining sidewalls and bottom surface of the trench and extending over mesa surfaces adjacent the trench;

after forming the dielectric layer, filling a lower portion of the trench with a shield electrode;

removing portions of the dielectric layer lining upper sidewalls of the trench and extending over the mesa surfaces adjacent the trench whereby a portion of the dielectric layer is recessed below a top surface of the shield electrode;

forming dielectric spacers along the upper trench sidewalls;

after forming the dielectric spacers, forming an inter-electrode dielectric (IED) in the trench over the shield electrode and adjacent the trench over the mesa surfaces; and

after forming the IED, removing the dielectric spacers.

2. The method of claim 1 further comprising forming a gate electrode in an upper portion of the trench, the gate electrode being insulated from the shield electrode by the IED.

3. The method of claim 2 wherein the semiconductor region has a first conductivity type, the method further comprising:

forming a body region of a second conductivity type in the semiconductor region; and

forming source regions of the first conductivity type in the body region flanking the trench.

4. The method of claim 3 wherein the semiconductor region comprises a substrate of the first conductivity type, the method further comprising:

forming an epitaxial layer of the first conductivity type over the substrate, wherein the body region is formed in the epitaxial layer, and the trench is formed so as to extend through the epitaxial layer and terminate within the substrate.

5. The method of claim 3 wherein the semiconductor region comprises a substrate of the first conductivity type, the method further comprising:

forming an epitaxial layer of the first conductivity type over the substrate, wherein the body region is formed in the epitaxial layer, and the trench is formed so as to extend into and terminate within the epitaxial layer.

6. A method of forming a field effect transistor comprising:

forming a trench in a semiconductor region;

forming a dielectric layer lining sidewalls and a bottom of the trench and extending over mesa surfaces adjacent the trench;

forming a shield electrode in a bottom portion of the trench, the shield electrode insulated from the semiconductor region by the dielectric layer;

removing portions of the dielectric layer lining upper sidewalls of the trench and extending over the mesa surfaces adjacent the trench whereby a portion of the dielectric layer is recessed below a top surface of the shield electrode;

forming dielectric spacers along upper trench sidewalls;

after forming the dielectric spacers, forming an inter-electrode dielectric (IED) in the trench over the shield electrode and adjacent the trench over the mesa surfaces; and

after forming the IED, removing the dielectric spacers.

7. The method of claim 6 further comprising forming a gate electrode in an upper portion of the trench, the gate electrode being insulated from the shield electrode by the IED.

8. The method of claim 6 wherein the semiconductor region has a first conductivity type, the method further comprising:

forming a body region of a second conductivity type in the semiconductor region; and

forming source regions of the first conductivity type in the body region flanking the trench.

9. The method of claim 8 wherein the semiconductor region comprises a substrate of the first conductivity type, the method further comprising:

forming an epitaxial layer of the first conductivity type over the substrate, wherein the body region is formed in the epitaxial layer, and the trench is formed so as to extend through the epitaxial layer and terminate within the substrate.

10. The method of claim 8 wherein the semiconductor region comprises a substrate of the first conductivity type, the method further comprising:

forming an epitaxial layer of the first conductivity type over the substrate, wherein the body region is formed in the epitaxial layer, and the trench is formed so as to extend into and terminate within the epitaxial layer.