Semiconductor device including n-type and p-type FinFET's constituting an inverter structure

• US 7,994,583 B2
• Filed: 05/12/2008
• Issued: 08/09/2011
• Est. Priority Date: 05/15/2007
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Inaba, Satoshi
• Primary Examiner(s): Fahmy; Wael M
• Assistant Examiner(s): Kalam; Abul
• Application Number:
  US12/119,070
• Publication Number:
  US 20080308848A1
• Time in Patent Office: 1,184 Days
• Field of Search: 257/369
• US Class Current: 257/369
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A semiconductor device according to an aspect of the invention comprises an n-type FinFET which is provided on a semiconductor substrate and which includes a first fin, a first gate electrode crossing a channel region of the first fin via a gate insulating film in three dimensions, and contact regions provided at both end of the first fin, a p-type FinFET which is provided on the semiconductor substrate and which includes a second fin, a second gate electrode crossing a channel region of the second fin via a gate insulating film in three dimensions, and contact regions provided at both end of the second fin, wherein the n- and the p-type FinFET constitute an inverter circuit, and the fin width of the contact region of the p-type FinFET is greater than the fin width of the channel region of the n-type FinFET.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

an n-type FinFET which is provided on the semiconductor substrate and which includes a first fin acting as an active region, a first gate electrode crossing a channel region of the first fin via a gate insulating film in three dimensions, and contact regions provided at one end and the other end of the first fin and sandwiching the channel region;

a p-type FinFET which is provided on the semiconductor substrate and which includes a second fin acting as an active region, a second gate electrode crossing a channel region of the second fin via a gate insulating film in three dimensions, and contact regions provided at one end and the other end of the second fin and sandwiching the channel region,

wherein the n-type FinFET and the p-type FinFET constitute an inverter circuit, and

a channel width of the p-type FinFET is equal to a channel width of the n-type FinFET,

the fin width of the contact region of the p-type FinFET to act as an output node of the inverter circuit is greater than the fin width of the channel region of the n-type FinFET,

a dimension in a direction parallel to a source-drain direction of the contact region, which acts as the output node of the inverter circuit, of the p-type FinFET is greater than a dimension in a direction parallel to a source-drain direction of the contact region, which acts as the output node of the inverter circuit, of the n-type FinFET, and

the fin width of the channel region of the p-type FinFET is greater than the fin width of the channel region of the n-type FinFET.

2. The semiconductor device according to claim 1, wherein the impurity concentration of the channel region of the p-type FinFET is higher than the impurity concentration of the channel region of the n-type FinFET.

3. The semiconductor device according to claim 1, further comprising an n-well region provided in the semiconductor substrate,

wherein the p-type FinFET is provided in the n-well region and a bias voltage is applied to the n-well region.

4. The semiconductor device according to claim 1, wherein the semiconductor substrate is composed of an SOI region and a bulk region and the n-type FinFET is arranged in the SOI region and the p-type FinFET is arranged in the bulk region.

5. The semiconductor device according to claim 1, wherein the channel plane of the n-type FinFET is an Si (100) plane and the channel plane of the p-type FinFET is an Si (110) plane.