Stacked semiconductor device

• US 7,994,620 B2
• Filed: 03/15/2007
• Issued: 08/09/2011
• Est. Priority Date: 03/16/2006
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Mukaida, Hideko, Yoshimura, Atsushi
• Primary Examiner(s): Sandvik; Benjamin P
• Assistant Examiner(s): Khan; Farid
• Application Number:
  US11/724,303
• Publication Number:
  US 20070222051A1
• Time in Patent Office: 1,608 Days
• Field of Search: 257/78, 257/666, 257723-725, 257/730, 257737-738, 257/777, 257782-787, 257685-686, 257/678, 257/E21.614, 257/E23.085, 257/E25.013, 257/E25.018, 257/E25.027, 438/107, 438/108, 438/118, 438/119, 361/735, 29/40, 21/44
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/20752 larger or equal to 20 microns less than 30 microns

Abstract

A stacked semiconductor device includes a first semiconductor element bonded on a circuit base. The first semiconductor element is electrically connected to a connection part of the circuit base via a first bonding wire. A second semiconductor element is bonded on the first semiconductor element via a second adhesive layer with a thickness of 50 μm or more. The second adhesive layer is formed of an insulating resin layer whose glass transition temperature is 135° C. or higher and whose coefficient of linear expansion at a temperature equal to or lower than the glass transition temperature is 100 ppm or less.

Claims

1. A stacked semiconductor device, comprising:

a circuit base having an element mounting part and a connection part;

a first semiconductor element bonded on the element mounting part of the circuit base;

a second semiconductor element bonded on the first semiconductor element via an adhesive layer with a thickness of 50 μ

m or more,

wherein the adhesive layer is formed of an insulating resin layer whose glass transition temperature is 135°

C. or higher and whose coefficient of linear expansion at a temperature equal to or lower than the glass transition temperature is 100 ppm or less and greater than zero ppm;

an electrode pad formed on the first semiconductor element and electrically connected to the connection part via a bonding wire, the electrode pad projecting from an upper face of the first semiconductor element, and an upper end of the electrode pad being in the adhesive layer; and

a sealing resin formed on the circuit base to seal the first and second semiconductor elements together with the bonding wire,

wherein a tensile stress acting on the first or second semiconductor element due to the adhesive layer during a thermal cycle test is 300 MPa or less and greater than zero MPa.

2. The stacked semiconductor device as set forth in claim 1,

wherein the adhesive layer has the thickness within a range from 70 μ

m to 150 μ

m.

3. The stacked semiconductor device as set forth in claim 1,

wherein each of the first and second semiconductor elements has a thickness of 70 μ

m or less.

4. The stacked semiconductor device as set forth in claim 3,

wherein the insulating resin layer has the coefficient of linear expansion of 70 ppm or lower at a temperature equal to or lower than the glass transition temperature.

5. The stacked semiconductor device as set forth in claim 1,

wherein the bonding wire is apart from a lower surface of the second semiconductor element due to the thickness of the adhesive layer.

6. The stacked semiconductor device as set forth in claim 5,

wherein the adhesive layer has a die bonding viscosity of not lower than 1 kPa·

s and lower than 100 kPa·

s.

7. The stacked semiconductor device as set forth in claim 1,

wherein the adhesive layer includes:

a first resin layer disposed on the first semiconductor element side and softening or melting at a temperature for bonding the second semiconductor element; and

a second resin layer disposed on the second semiconductor element side and maintaining a layered form at the temperature for bonding the second semiconductor element,

wherein the end portion of the bonding wire is buried in the first resin layer.

8. The stacked semiconductor device as set forth in claim 7,

wherein the first resin layer has a die bonding viscosity of not lower than 1 kPa·

s and lower than 100 kPa·

s, and

wherein the second resin layer has a die bonding viscosity of 100 kPa·

s or higher.

9. The stacked semiconductor device as set forth in claim 1,

wherein the second semiconductor element has a substantially same shape as the first semiconductor element or a shape larger than the first semiconductor element.

10. The stacked semiconductor device as set forth in claim 1,

wherein the circuit base has an external connection terminal which is formed on a surface opposite a surface where the element mounting part is provided.

11. The stacked semiconductor device as set forth in claim 1,

wherein the electrode pad is a stud bump.

12. The stacked semiconductor device as set forth in claim 1,

wherein the thermal cycle test is carried from −

55°

C. to 125°

C.