Efficient reloading of data into cache resource

• US 8,443,150 B1
• Filed: 09/24/2010
• Issued: 05/14/2013
• Est. Priority Date: 11/04/2008
• Status: Active Grant

• Current Assignee: Innovations In Memory LLC
• Original Assignee: Violin Memory Incorporated
• Inventors: de la Iglesia, Erik
• Primary Examiner(s): YU, JAE UN
• Application Number:
  US12/889,732
• Time in Patent Office: 963 Days
• Field of Search: 711/118, 711/133, 711/135, 711/144
• US Class Current: 711/135
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means

Abstract

A storage proxy includes a cache resource. A processor is configured to receive read and write requests sent from an initiator to a target over a first proxy path. The processor invalidates the cache lines when the read and write requests are redirected over a second direct path between the initiator and the target or when some other event indicates the data in the cache lines may no longer be consistent with corresponding data in the target. The processor identifies addresses for at least some of the cache lines that were previously valid and reloads the data for the identified addresses from the target back into some the cache lines when the read and write requests are redirected back over the first proxy path or when consistency can resumed between the data in the cache lines and corresponding data in the target.

Claims

1. An apparatus, comprising:

cache lines configured to store copies of data from a storage target; and

logic circuitry configured to invalidate the cache lines when the copies of the data in the cache resource may be inconsistent with the data in the storage target, the logic circuit further configured to identify addresses for at least some cache lines that were previously valid and reload copies of the data at the identified addresses from the storage target into some of the cache lines.

2. The apparatus of claim 1 wherein the logic circuitry is configured to invalidate the cache lines when storage access requests can no longer be monitored and reload copies of data from the storage target into the cache lines when the storage access requests can start being monitored.

3. The apparatus of claim 1 wherein the cache lines include read count values identifying a number of times the cache lines were read over a predetermined time period and last timestamp values identifying a last time and the cache lines were read.

4. The apparatus of claim 3 wherein the logic circuitry is configured to identify the previously valid cache lines according to the read count values and last timestamp values.

5. The apparatus of claim 1 wherein the logic circuitry is configured to derive an address range that includes the addresses for multiple previously valid cache lines and upload the data located at the address range from the storage target into the cache lines.

6. The apparatus of claim 5 wherein the logic circuitry is configured to upload the data from the storage target to the cache lines when the address range reaches a threshold value.

8. The apparatus of claim 1 further comprising a cluster map identifying a cluster address range for a contiguous set of the cache lines, wherein the logic circuitry is configured to reload data at the cluster address range in the storage target into the cache lines.

9. The apparatus of claim 8 wherein the cluster map includes:

a read count value identifying a number of times the contiguous set of cache lines was read; and

a last timestamp value identifying a last time the contiguous set of cache lines was read.

10. The apparatus of claim 9 wherein the logic circuitry is configured to identify the cluster address range according to the read count value and the last timestamp value.

7. The apparatus according 1 wherein the logic circuitry is configured to:

identify a first address associated with a first previously valid cache line;

identify an address range that includes the first address;

identify a second address associated with a second previously valid cache line;

extend the address range to include the second address when a gap between the first address and the second address range is under a threshold; and

extend the address range to only include the second address when a gap between the first address and the second address range is over a threshold.

11. A computer readable medium containing instructions configured to be executed by a computer system, the instructions when executed by the computer system comprising:

loading data from a storage disk into cache lines in a cache resource;

invalidating the cache lines when a condition is detected where consistency might not be maintained between the data in the cache resource and corresponding data in the storage disk;

identifying addresses for previously valid cache lines; and

reloading data corresponding with the addresses from the storage disk into some of the cache lines when consistency can be maintained between the data in the cache resource and the corresponding data in the storage disk.

12. The computer readable medium according to claim 11 further comprising:

tracking read count values for the cache lines;

identifying last timestamp values for the cache lines; and

identifying the previously valid cache lines according to the read count values and last timestamp values.

13. The computer readable medium according to claim 11 further comprising:

identifying a first address associated with a first one of the previously valid cache lines;

identifying a second address associated with a second one of the previously valid cache lines;

identifying an address range that includes the first address and the second address; and

uploading data within the address range in the storage disk into the cache lines.

14. The computer readable medium according to claim 13 further comprising uploading the data from the storage disk into the cache lines when the address range reaches a size limit.

15. The computer readable medium according to claim 13 further comprising:

identifying an address gap between the first address and the second address;

modifying the address range to begin at the second address and not include the first address when the address gap is above a threshold.

16. The computer readable medium according to claim 11 further comprising:

identifying a cluster of cache lines;

identify an address range that extends over addresses associated with the cluster of cache lines; and

uploading data within the address range in the storage disk into the cache lines.

17. The computer readable medium according to claim 16 further comprising uploading the data within the address range when a read count value for the cluster of cache lines is above a count threshold and a last timestamp value for the cluster of cache lines is less than a time threshold.

18. The computer readable medium according to claim 11 further comprising:

identifying a first cluster of cache lines;

identifying a first address range for the first cluster of cache lines;

identifying a second cluster of cache lines;

identifying a second address range for the second cluster of cache lines;

identifying a third address range that extends over the first address range and the second address range; and

uploading data for the third storage range in the storage disk into the cache lines.

19. A storage proxy, comprising:

a cache resource including cache lines; and

a processor configured to receive storage access requests sent over a first proxy path from an initiator to a target and invalidate the cache lines when the storage access requests are redirected over a second direct path between the initiator and the target, the processor further configured to identify addresses for at least some of the cache lines that were previously valid and reload the data from the target at the identified addresses into some of the cache lines.

20. The storage proxy of claim 19 wherein the processor is configured to identify the cache lines that were previously valid according to a number of times the cache lines were read.

21. The storage proxy according to claim 20 wherein the processor is configured to identify the cache lines that were previously valid according to when the cache lines were last read.

22. The storage proxy according to claim 20 wherein the processor is configured to:

identify a first address for a first one of the cache lines that was previously valid;

identify an address range that includes the first address;

identify a second address for a second one of the cache lines that was previously valid;

extend the address range to extend from the first address to the second address; and

upload data located at the address range in the target to the cache lines when the address range reaches a threshold.