MEMS device having chip scale packaging

• US 8,525,278 B2
• Filed: 08/19/2011
• Issued: 09/03/2013
• Est. Priority Date: 08/19/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chu, Chia-Hua, Lin, Chung-Hsien
• Primary Examiner(s): Mandala, Victor A
• Assistant Examiner(s): MOORE, WHITNEY
• Application Number:
  US13/213,863
• Publication Number:
  US 20130043547A1
• Time in Patent Office: 746 Days
• Field of Search: 257/415, 257/254, 257/777, 257/E21.705, 257/E27.006, 438/48, 438/51, 438/121
• US Class Current: 257/415
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 2201/0242 Gyroscopes
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/0362 Photolithography
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/06181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/1145 : Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11452 : Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/1146 : Plating
• CPC Class Codes: H01L 2224/11622 : Photolithography
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13109 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13164 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/13166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81011 : Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/81013 : Plasma cleaning
• CPC Class Codes: H01L 2224/81054 : Composition of the atmosphere
• CPC Class Codes: H01L 2224/81065 : being reducing
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/8182 : Diffusion bonding
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/10 : characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/1461 : MEMS

Abstract

A method and device having chip scale MEMS packaging is described. A first substrate includes a MEMS device and a second substrate includes an integrated circuit. The frontside of the first substrate is bonded to the backside of the second substrate. Thus, the second substrate provides a cavity to encase, protect or operate the MEMS device within. The bond may provide an electrical connection between the first and second substrate. In an embodiment, a through silicon via is used to carry the signals from the first substrate to an I/O connection on the frontside of the second substrate.

Claims

1. A device, comprising:

a first substrate having a MEMS device disposed on a frontside of the first substrate;

a second substrate including an integrated circuit (IC) and having a frontside and an opposing backside, wherein the IC includes a multi-layer interconnect (MLI) structure, wherein the MLI structure includes;

a first conductive line,

a second conductive line overlying the first conductive line,

a conductive via connecting the first and second conductive line,

a dielectric material interposing the first and second conductive lines;

and wherein the second substrate further includes a through-silicon via (TSV) extending from the backside of the second substrate to the first conductive line;

wherein a first bonding feature on the frontside of the first substrate is bonded to a second bonding feature on a backside of the second substrate; and

wherein the TSV connects the second bonding feature and the first conductive line.

2. The device of claim 1, wherein the second substrate further includes a recess formed in the backside of the second substrate.

3. The device of claim 1, wherein the bonded first bonding feature and the bonded second bonding feature form a seal ring surrounding a cavity, wherein the MEMS device is disposed in the cavity.

4. The device of claim 1, wherein the second substrate includes an input/output (I/O) pad formed on the frontside of the second substrate, wherein the I/O pad is electrically connected to the MLI structure.

5. The device of claim 4, wherein at least one of a wire bond and a bump are connected to the I/O pad.

6. The device of claim 1, further comprising:

a dielectric layer disposed on the backside of the second substrate including underlying the first bonding element.

7. The device of claim 6, wherein the dielectric layer is formed on the backside of the second substrate and not the frontside of the second substrate.

8. A method, comprising:

providing a first substrate having a MEMS device disposed on a frontside of the first substrate;

providing a second substrate including an integrated circuit and having a backside and an opposing frontside, wherein a multilayer interconnect (MLI) structure is disposed on the frontside of the second substrate, wherein the MLI structure includes a plurality of conductive lines interposed by dielectric material;

forming a first bonding feature on the frontside of the first substrate;

forming a second bonding feature on the backside of second substrate;

forming a through-silicon via (TSV) on the second substrate connecting the second bonding feature and the conductive lines of the MLI structure, wherein the forming the TSV on the second substrate includes exposing a bottom surface of the one of the conductive lines of the MLI structure, wherein another one of the conductive lines of the MLI structure overlies the one of the conductive lines of the MLI structure; and

wherein the TSV provides for connecting the second bonding feature and an I/O pad formed on the frontside of the second substrate; and

providing an electrical connection between the first substrate and the second substrate by connecting the first bonding feature and the second bonding feature.

9. The method of claim 8, further comprising:

wire bonding to the I/O pad formed on the frontside of the second substrate.

10. The method of claim 8, further comprising:

forming a conductive bump on the I/O pad formed on the frontside of the second substrate.

11. The method of claim 8, further comprising:

etching a recess in the backside of the second substrate prior to providing the electrical connection.

12. The method of claim 8, further comprising:

forming a layer of passivation on a surface of the frontside of the second substrate.

13. The method of claim 8, wherein the connecting the first bonding feature and the second bonding feature forms a cavity between the frontside of the first substrate and the backside of the second substrate, and wherein the MEMS device is disposed in the cavity.

14. The method of claim 13, wherein the cavity is between approximately 0.1 microns and approximately 100 microns in height.

15. A method, comprising:

providing a first substrate having a MEMS device disposed on a frontside of the first substrate;

providing a second substrate including features of a circuit formed on a frontside of the second substrate;

etching a recess in a backside of the second substrate;

forming a dielectric layer on the backside of the second substrate including in the etched recess; and

bonding the frontside of the first substrate and the backside of the second substrate such that the MEMS device is disposed a cavity defined by the recess, wherein the dielectric layer lines a surface of the cavity.

16. The method of claim 15, wherein the bonding includes:

forming a first bonding feature on the frontside of the first substrate;

forming a second bonding feature on the backside of the second substrate; and

electrically coupling the first bonding feature to a second bonding feature.

17. The method of claim 15, wherein the bonding includes creating a vacuum environment in the cavity, and wherein the dielectric layer is included in the cavity.

18. The method of claim 15, wherein the bonding includes forming a eutectic bond.

19. The method of claim 15, further comprising:

forming a through silicon via extending from the backside of the second substrate to a conductive surface on the second substrate, prior to forming the dielectric layer; and

after forming the dielectric layer, removing the dielectric layer from the conductive surface on the second substrate.