Formation of embedded stressor through ion implantation
First Claim
1. A method for fabricating an extremely-thin-silicon-on-insulator transistor, the method comprising:
- forming a buried oxide layer on a silicon substrate;
forming a silicon layer on the buried oxide layer;
forming a gate stack on the silicon layer that is above the buried oxide layer;
forming a gate spacer on the silicon layer and on sidewalls of the gate stack;
epitaxially forming a first raised source/drain region and a second raised source/drain region each adjacent to the gate spacer; and
forming at least one embedded stressor at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer, wherein the at least one embedded stressor is substantially aligned with at least one of the gate stack, and one or more of the first and second raised source/drain regions.
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Accused Products
Abstract
An extremely-thin silicon-on-insulator transistor includes a buried oxide layer above a substrate. The buried oxide layer, for example, has a thickness that is less than 50 nm. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer includes at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric. A gate spacer has a first part on the silicon layer and a second part adjacent to the gate stack. A first raised source/drain region and a second raised source/drain region each have a first part that includes a portion of the silicon layer and a second part adjacent to the gate spacer. At least one embedded stressor is formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer.
25 Citations
9 Claims
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1. A method for fabricating an extremely-thin-silicon-on-insulator transistor, the method comprising:
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forming a buried oxide layer on a silicon substrate; forming a silicon layer on the buried oxide layer; forming a gate stack on the silicon layer that is above the buried oxide layer; forming a gate spacer on the silicon layer and on sidewalls of the gate stack; epitaxially forming a first raised source/drain region and a second raised source/drain region each adjacent to the gate spacer; and forming at least one embedded stressor at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer, wherein the at least one embedded stressor is substantially aligned with at least one of the gate stack, and one or more of the first and second raised source/drain regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification