Resistive memory
First Claim
1. A circuit, comprising:
- a multiplexer having an output coupled to an intermediate potential through a resistive element during operation of the circuit;
one or more pairs of first transistors coupled between a potential greater than the intermediate potential and a corresponding at least one input of the multiplexer; and
one or more pairs of second transistors coupled between a potential less than the intermediate potential and a corresponding at least one input of the multiplexer,wherein the multiplexer is configured to select at least one of a number of currents that respectively flow through at least one of the pairs of first transistors or pairs of second transistors in response to a selection signal for programming the resistive element, each of the number of currents having a unique combination of current direction and magnitude.
8 Assignments
0 Petitions
Accused Products
Abstract
The present disclosure includes resistive memory devices and systems having resistive memory cells, as well as methods for operating the resistive memory cells. One memory device embodiment includes at least one resistive memory element, a programming circuit, and a sensing circuit. For example, the programming circuit can include a switch configured to select one of N programming currents for programming the at least one resistive memory element, where each of the N programming currents has a unique combination of current direction and magnitude, with N corresponding to the number of resistance states of the at least one memory element. In one or more embodiments, the sensing circuit can be arranged for sensing of the N resistance states.
31 Citations
20 Claims
-
1. A circuit, comprising:
-
a multiplexer having an output coupled to an intermediate potential through a resistive element during operation of the circuit; one or more pairs of first transistors coupled between a potential greater than the intermediate potential and a corresponding at least one input of the multiplexer; and one or more pairs of second transistors coupled between a potential less than the intermediate potential and a corresponding at least one input of the multiplexer, wherein the multiplexer is configured to select at least one of a number of currents that respectively flow through at least one of the pairs of first transistors or pairs of second transistors in response to a selection signal for programming the resistive element, each of the number of currents having a unique combination of current direction and magnitude. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A circuit, comprising:
-
a multiplexer having an output coupled to a bit line; a resistive element having a first terminal coupled to the bit line associated with the resistive element and a second terminal coupled to a first terminal of an access transistor, a gate of the access transistor coupled to a word line associated with the resistive element, a second terminal of the access transistor coupled to an intermediate potential; first transistors coupled between a potential greater than the intermediate potential and a respective input of the multiplexer; and second transistors coupled between a potential less than the intermediate potential and a respective input of the multiplexer, wherein the multiplexer is configured to selectably couple one of the first transistors or the second transistors to the output of the multiplexer. - View Dependent Claims (15, 16, 17)
-
-
18. A circuit, comprising:
-
a resistive element having a first terminal coupled to the bit line and a second terminal coupled to a first terminal of an access transistor, a gate of the access transistor coupled to a word line associated with the resistive element, a second terminal of the access transistor coupled to an intermediate potential; a multiplexer having an output coupled to the bit line; a first pair of series-coupled first transistors coupled in parallel between a potential greater than the intermediate potential and a first multiplexer input; and a first pair of series-coupled second transistors coupled in parallel between a potential less than the intermediate potential and a second multiplexer input. - View Dependent Claims (19, 20)
-
Specification