Magnetoresistive random access memory

• US 8,796,045 B2
• Filed: 11/29/2012
• Issued: 08/05/2014
• Est. Priority Date: 11/06/2012
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Worledge, Daniel C.
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US13/689,102
• Publication Number:
  US 20140127831A1
• Time in Patent Office: 614 Days
• Field of Search: 438/3, 257/E29.179, 257/E21.665
• US Class Current: 438/3
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment

Abstract

A method of forming a magnetic random access memory (MRAM) device includes forming at least one write line, forming a first insulating layer over the at least one write line and forming a heating line on the first insulating layer. The method includes forming at least one tunnel junction above the at least one write line, the at least one tunnel junction connected to the heating line, forming a second insulating layer on the heating line and forming heat current supply vias at each end of the current line. The method further includes forming heat current supply lines connected to each heat current supply via and forming at least one read line above the at least one tunnel junction and physically connected to the at least one tunnel junction.

Claims

1. A method of forming a magnetic random access memory (MRAM) device, comprising:

forming at least one write line;

forming a first insulating layer over the at least one write line;

forming a heating line on the first insulating layer;

forming at least one tunnel junction above the at least one write line, the at least one tunnel junction connected to the heating line;

forming a second insulating layer on the heating line;

forming heat heating supply vias at each end of the current line;

forming heat current supply lines connected to each heat current supply via; and

forming at least one read line above the at least one tunnel junction and physically connected to the at least one tunnel junction, wherein the at least read line, at least one tunnel junction and at least one write line include a plurality of read lines, tunnel junctions and write lines, respectively, the method further comprising;

forming the heating line to have a larger width between two adjacent tunnel junctions than adjacent to each tunnel junction.

2. The method of claim 1, wherein the heat current supply lines are on a same metal layer as the at least one read line.

3. The method of claim 1, wherein the at least one write line has a cross-sectional area greater than a cross-sectional area of the at least one read line.

4. The method of claim 1, wherein the heat current supply vias have cross-sectional widths greater than a cross-sectional width of the at least one tunnel junction.

5. The method of claim 1, wherein the heat current supply vias have cross-sectional widths that are substantially the same as cross-sectional widths of the heat current supply lines.

6. The method of claim 1, further comprising:

forming first and second main heat current supply lines; and

alternatingly connecting the first and second main heat current supply lines to the heat current supply lines connected in series with the heating line.

7. The method of claim 6, wherein alternatingly connecting the first and second main heat current supply lines to the heat current supply lines connected in series with the heating line comprises:

forming a plurality of transistors, each transistor having one of a source and a drain connected to a separate heat current supply line and the other of the source and the drain connected to one of the first and second main heat current supply lines.

8. The method of claim 7, further comprising:

forming vias to connect the plurality of transistors to the heat current supply lines and the first and second main heat current supply lines.

9. A method of forming a magnetic random access memory (MRAM) device, comprising:

forming at least one write line;

forming a first insulating layer over the at least one write line;

forming a heating line on the first insulating layer;

forming at least one tunnel junction above the at least one write line, the at least one tunnel junction connected to the heating line;

forming a second insulating layer on the heating line;

forming heat current supply vias at each end of the heating line;

forming heat current supply lines connected to each heat current supply via; and

forming at least one read line above the at least one tunnel junction and physically connected to the at least one tunnel junction, wherein the heating line is formed using one first mask and the tunnel junctions and heat current supply vias are formed using one second mask.