Apparatuses, device, and methods for cleaning tester interface contact elements and support hardware

• US 8,801,869 B2
• Filed: 11/04/2011
• Issued: 08/12/2014
• Est. Priority Date: 12/03/2009
• Status: Active Grant

• Current Assignee: Entegris Incorporated
• Original Assignee: International Test Solutions Incorporated (International Test Solutions)
• Inventors: Broz, Jerry J., Humphrey, Bret A., Humphrey, Alan E., Duvall, James H.
• Primary Examiner(s): GOLIGHTLY, ERIC WAYNE
• Application Number:
  US13/290,015
• Publication Number:
  US 20120042463A1
• Time in Patent Office: 1,012 Days
• Field of Search: None
• US Class Current: 134/166.R
• CPC Class Codes: B08B 1/00 Cleaning by methods involving the use of tools cleaning hollow articles by methods or apparatus specially adapted thereto B08B9/00
• CPC Class Codes: B08B 7/0028 by adhesive surfaces
• CPC Class Codes: B24B 19/16 for grinding sharp-pointed workpieces, e.g. needles, pens, fish hooks, tweezers or record player styli grinding bevels on diamonds or sapphires B24B9/16; polishing of needles B24B29/08
• CPC Class Codes: B24D 11/005 Making abrasive webs
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips

Abstract

A cleaning device for cleaning pin contact elements and support hardware in a semiconductor testing apparatus that has a cleaning layer with a predetermined configuration appropriate for the particular pin contact elements and a substrate having a configuration to be introduced into the testing apparatus during the normal testing operating of the testing apparatus. The cleaning layer secured to the substrate has predetermined characteristics that cause the pad to clean debris the pin contact elements and support hardware when the pin contact elements and support hardware contact the pad during the normal operation of the testing machine.

Claims

1. A cleaning device for cleaning pin contact elements and support hardware in a semiconductor testing apparatus, the cleaning device comprising:

a cleaning layer with a configuration for the pin contact elements, the cleaning layer having a plurality of geometric micro-features that extend above a surface of the cleaning layer with predetermined geometrical and dimensional properties;

a substrate having a configuration to be introduced into the testing apparatus during the normal testing operating of the testing apparatus, wherein the substrate comprises a surrogate semiconductor wafer or packaged IC device;

the cleaning layer, secured to the substrate, having predetermined characteristics that clean debris from the pin contact elements and support hardware when the pin contact elements and support hardware contact the cleaning layer so that the pin contact elements and support hardware are cleaned during a normal operation of the testing machine.

2. The device of claim 1 further comprising one or more intermediate layers that provide one or more of an abrasiveness, a specific gravity, an elasticity, tackiness, planarity, thickness and a porosity.

3. The device of claim 2, wherein the cleaning layer provides one or more of an abrasiveness, a specific gravity, an elasticity, tackiness, planarity, thickness and a porosity.

4. A cleaning device for cleaning pin contact elements and support hardware in a semiconductor testing apparatus, the cleaning device comprising:

a cleaning layer with a configuration for the pin contact elements, the cleaning layer having a plurality of geometric micro-features that extend above a surface of the cleaning layer with geometrical and dimensional properties so that a contact area and surrounding support hardware are cleaned without modification or damage and wherein the cleaning layer further comprises a plurality of abrasive particles having a Mohs Hardness of 7 or greater for cleaning contact elements and support structures of testing interfaces;

a substrate having a configuration to be introduced into the testing apparatus during normal testing operating of the testing apparatus, wherein the substrate comprises a surrogate semiconductor wafer or packaged IC device; and

the cleaning layer, secured to the substrate, having characteristics that clean debris from the pin contact elements and support hardware when the pin contact elements and support hardware contact the cleaning layer so that the pin contact elements and support hardware are cleaned, without modification to normal operation of the testing machine.

5. The device of claim 4, wherein each geometric micro-feature is uniformly shaped and regularly spaced from each other geometric micro-feature.

6. The device of claim 4, wherein the plurality of abrasive particles are applied to one of a top surface of each micro-feature, along the sides of each micro-feature and on faces of each micro-feature.

7. The device of claim 4, wherein each micro-feature has a body and the plurality of abrasive particles are distributed within the body of each micro-feature.

8. The device of claim 4, wherein each micro-feature has a base and the plurality of abrasive particles are applied at the base of each micro-feature.