Controller to execute error correcting code algorithms and manage NAND memories
First Claim
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1. A storage system to couple to a host, the storage system comprising:
- a plurality of NAND memory devices, the plurality of NAND memory devices not internally implementing an error correcting code (ECC) algorithm; and
a controller external to the plurality of NAND memory devices, the controller to export to the host a virtualized address space to allow the host to drive the storage system as a single NAND memory device even though the storage system includes a plurality of NAND memory devices, the controller further to provide a single virtualized ECC algorithm for each of the plurality of NAND memory devices.
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Abstract
A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.
25 Citations
20 Claims
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1. A storage system to couple to a host, the storage system comprising:
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a plurality of NAND memory devices, the plurality of NAND memory devices not internally implementing an error correcting code (ECC) algorithm; and a controller external to the plurality of NAND memory devices, the controller to export to the host a virtualized address space to allow the host to drive the storage system as a single NAND memory device even though the storage system includes a plurality of NAND memory devices, the controller further to provide a single virtualized ECC algorithm for each of the plurality of NAND memory devices. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A controller to interface with a plurality of NAND memory devices in a storage system, the controller comprising:
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a protocol interface circuit to exchange signals with a host processor; an Error Correcting Code (ECC) engine to implement an ECC algorithm; and a NAND interface to manage the plurality of NAND memory devices, the NAND interface configured to emulate commands issued by the host processor that are not supported by the plurality of NAND memory devices, the NAND interface further configured to provide power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A method of managing a stack of NAND memory devices that do not internally implement an Error Correcting Code (ECC) algorithm, the method comprising:
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using a protocol interface block of a controller device to exchange signals with a host processor to allow the host processor to communicate with a large error free address space; implementing a single virtualized ECC algorithm by an ECC engine block embedded in the controller device; and re-elaborating both commands and addresses received from the host processor by a NAND interface block embedded in the controller device to manage data transfers to the stack of NAND memory devices. - View Dependent Claims (15, 16)
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17. A wireless communication system including multiple NAND memory devices, the wireless communication system comprising:
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a transceiver; a processor having first and second processor cores, the processor being coupled to the transceiver; and an Error Correcting Code (ECC) controller having an embedded NAND interface block to receive commands and addresses and exchange signals with the processor, an ECC engine to implement an ECC algorithm, and a NAND interface circuit to re-elaborate both commands and addresses received from the host processor to direct data transfers with the multiple NAND memory devices, the multiple NAND memory devices not internally implementing an ECC algorithm. - View Dependent Claims (18, 19, 20)
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Specification