Method for epitaxial re-growth of semiconductor region

• US 8,815,712 B2
• Filed: 03/07/2012
• Issued: 08/26/2014
• Est. Priority Date: 12/28/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wan, Cheng-Tien, Lin, You-Ru, Lee, Yi-Jing, Wu, Cheng-Hsien, Ko, Chih-Hsin, Wann, Clement Hsingjen
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): DUONG, KHANH B
• Application Number:
  US13/414,357
• Publication Number:
  US 20130171792A1
• Time in Patent Office: 902 Days
• Field of Search: None
• US Class Current: 438/478
• CPC Class Codes: H01L 21/02057 Cleaning during device manufacture
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region.

Claims

1. A method comprising:

forming Shallow Trench Isolation (STI) regions extending from a top surface of a semiconductor substrate into the semiconductor substrate;

etching a portion of the semiconductor substrate between opposite sidewalls of the STI regions to form a recess;

performing a treatment on a surface of the semiconductor substrate, with the surface being in the recess, wherein the treatment is performed using process gases comprising;

an oxygen-containing gas; and

an etching gas capable of etching the semiconductor substrate;

performing an epitaxy to grow a second semiconductor region starting from the surface; and

after the performing the epitaxy, recessing the STI regions.

2. The method of claim 1, wherein the oxygen-containing gas is selected from the group consisting essentially of oxygen (O₂), ozone (O₃), and combinations thereof.

3. The method of claim 1, wherein the oxygen-containing gas comprises O₂.

4. The method of claim 1 further comprising, before the performing the epitaxy and after the treatment, performing a cleaning on the surface.

5. The method of claim 1, wherein the treatment comprises a plasma treatment.

6. The method of claim 1, wherein the performing the epitaxy to grow the second semiconductor region comprises growing a III-V compound semiconductor material.

7. The method of claim 1, wherein the etching gas comprises CF₄.

8. The method of claim 1, wherein a top portion of the second semiconductor region over the recessed STI regions forms a fin;

forming a gate dielectric on sidewalls and a top surface of the fin; and

forming a gate electrode over the gate dielectric.

9. A method comprising:

forming Shallow Trench Isolation (STI) regions extending from a top surface of a semiconductor substrate into the semiconductor substrate;

etching a portion of the semiconductor substrate between opposite sidewalls of the STI regions to form a recess, wherein the portion of the semiconductor substrate comprises a top surface in the recess;

performing a treatment on the top surface, wherein the treatment is performed using process gases comprising;

an oxygen-containing gas; and

an etching gas capable of etching the semiconductor substrate;

after the treatment, performing a cleaning on the top surface; and

after the treatment, performing an epitaxy to grow a semiconductor region in the recess;

after the epitaxy, recessing the STI regions.

10. The method of claim 9 further comprising:

before the step of etching the semiconductor substrate, forming a gate stack of a transistor over the semiconductor substrate; and

forming spacers on opposite sidewalls of the gate stack, wherein the step of etching is performed using the spacers as an etching mask, and wherein the semiconductor region forms a source/drain stressor region of the transistor.

11. The method of claim 9, wherein the oxygen-containing gas comprises oxygen (O₂), and wherein the etching gas comprises CF₄.

12. The method of claim 11, wherein the cleaning is performed using a solution comprising diluted HF.

13. The method of claim 12, wherein a flow-rate ratio of a flow rate of O₂ to a total flow rate of CF₄ and O₂ is greater than about 1 percent.

14. The method of claim 11, wherein the treatment comprises a plasma treatment.

15. The method of claim 9, wherein the performing the epitaxy to grow the semiconductor region comprises growing a III-V compound semiconductor material.

16. A method comprising:

forming Shallow Trench Isolation (STI) regions extending from a first top surface of a silicon substrate into the silicon substrate;

etching a portion of the silicon substrate between opposite sidewalls of the STI regions to form a recess, wherein the silicon substrate comprises a second top surface in the recess;

performing a treatment on the second top surface, wherein the treatment is performed using process gases comprising CF₄ and O₂;

after the treatment, performing a cleaning on the second top surface of the silicon substrate;

performing an epitaxy to grow a germanium-containing semiconductor region in the recess, wherein the germanium-containing semiconductor region is grown from the second top surface in the recess; and

forming a Fin Field-Effect Transistor (FinFET) comprising;

after the epitaxy, recessing the STI regions, wherein a top portion of the germanium-containing semiconductor region over the recessed STI regions forms a fin;

forming a gate dielectric on sidewalls and a top surface of the fin; and

forming a gate electrode over the gate dielectric.

17. The method of claim 16, wherein a flow-rate ratio of a flow rate of O₂ to a total flow rate of CF₄ and O₂ is greater than about 1 percent.

18. The method of claim 16, wherein the treatment comprises a plasma treatment.

19. The method of claim 16, wherein during the treatment, the silicon substrate is heated to a temperature between about 150°

C. and about 300°

C.

20. The method of claim 16, wherein the cleaning is performed using diluted HF solution.