Graphics processor with arithmetic and elementary function units
First Claim
1. An apparatus comprising:
- an output buffer;
at least one arithmetic logic unit (ALU) operative to perform arithmetic operations based on ALU instructions of one thread; and
at least one elementary function unit operative to compute elementary functions based on elementary function unit instructions of the one thread, wherein the at least one elementary function unit and the at least one ALU are independently coupled to the output buffer and are configured to operate on different instructions of the one thread in parallel, and wherein the ALU instructions of the one thread comprise synchronization bits, as part of the ALU instructions of the one thread, that ensure that the ALU instructions of the one thread that are dependent upon the elementary function unit instructions of the one thread follow the elementary function unit instructions of the one thread upon which the ALU instructions of the one thread depend.
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Accused Products
Abstract
A graphics processor capable of efficiently performing arithmetic operations and computing elementary functions is described. The graphics processor has at least one arithmetic logic unit (ALU) that can perform arithmetic operations and at least one elementary function unit that can compute elementary functions. The ALU(s) and elementary function unit(s) may be arranged such that they can operate in parallel to improve throughput. The graphics processor may also include fewer elementary function units than ALUs, e.g., four ALUs and a single elementary function unit. The four ALUs may perform an arithmetic operation on (1) four components of an attribute for one pixel or (2) one component of an attribute for four pixels. The single elementary function unit may operate on one component of one pixel at a time. The use of a single elementary function unit may reduce cost while still providing good performance.
136 Citations
43 Claims
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1. An apparatus comprising:
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an output buffer; at least one arithmetic logic unit (ALU) operative to perform arithmetic operations based on ALU instructions of one thread; and at least one elementary function unit operative to compute elementary functions based on elementary function unit instructions of the one thread, wherein the at least one elementary function unit and the at least one ALU are independently coupled to the output buffer and are configured to operate on different instructions of the one thread in parallel, and wherein the ALU instructions of the one thread comprise synchronization bits, as part of the ALU instructions of the one thread, that ensure that the ALU instructions of the one thread that are dependent upon the elementary function unit instructions of the one thread follow the elementary function unit instructions of the one thread upon which the ALU instructions of the one thread depend. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. An integrated circuit comprising:
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an output buffer; at least one arithmetic logic unit (ALU) operative to perform arithmetic operations based on ALU instructions of one thread; and at least one elementary function unit operative to compute elementary functions based on elementary function unit instructions of the one thread, wherein the at least one elementary function unit and the at least one ALU are independently coupled to the output buffer and are configured to operate on different instructions of the one thread in parallel, and wherein the ALU instructions of the one thread comprise synchronization bits, as part of the ALU instructions of the one thread, that ensure that the ALU instructions of the one thread that are dependent upon the elementary function unit instructions of the one thread follow the elementary function unit instructions of the one thread upon which the ALU instructions of the one thread depend. - View Dependent Claims (15, 16, 17)
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18. A wireless device comprising:
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a graphics processor comprising; an output buffer; at least one arithmetic logic unit (ALU) operative to perform arithmetic operations based on ALU instructions of one thread; and at least one elementary function unit operative to compute elementary functions based on elementary function unit instructions of the one thread, wherein the at least one elementary function unit and the at least one ALU are independently coupled to the output buffer and are configured to operate on different instructions of the one thread in parallel, and wherein the ALU instructions of the one thread comprise synchronization bits, as part of the ALU instructions of the one thread, that ensure that the ALU instructions of the one thread that are dependent upon the elementary function unit instructions of the one thread follow the elementary function unit instructions of the one thread upon which the ALU instructions of the one thread depend; and a memory system operative to store data for the graphics processor. - View Dependent Claims (19)
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20. A method comprising:
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performing, with at least one arithmetic logic unit (ALU), arithmetic operations based on ALU instructions of one thread; and computing, with at least one elementary function unit, elementary functions based on elementary function unit instructions of the one thread; wherein the ALU and the elementary function unit are independently coupled to an output buffer and operate on different instructions of the one thread in parallel, and wherein the ALU instructions of the one thread comprise synchronization bits, as part of the ALU instructions of the one thread, that ensure that the ALU instructions of the one thread that are dependent upon the elementary function unit instructions of the one thread follow the elementary function unit instructions of the one thread upon which the ALU instructions of the one thread depend. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28)
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29. An apparatus comprising:
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an output buffer; means for performing arithmetic operations based on arithmetic logic unit (ALU) instructions of one thread; and means for computing elementary functions based on elementary function unit instructions of the one thread, wherein the means for performing and the means for computing are independently coupled to the output buffer and are configured to operate on different instructions of the one thread in parallel, and wherein the ALU instructions of the one thread comprise synchronization bits, as part of the ALU instructions of the one thread, that ensure that the ALU instructions of the one thread that are dependent upon the elementary function unit instructions of the one thread follow the elementary function unit instructions of the one thread upon which the ALU instructions of the one thread depend. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36)
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37. A non-transitory computer-readable storage medium having stored thereon instructions, when executed, cause one or more processors to:
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perform, with at least one arithmetic logic unit (ALU), arithmetic operations based on ALU instructions of one thread; and compute, with at least one elementary function unit, elementary functions based on elementary function unit instructions of the one thread; wherein the ALU and the elementary function unit are independently coupled to an output buffer and operate on different instructions of the one thread in parallel, and wherein the ALU instructions of the one thread comprise synchronization bits, as part of the ALU instructions of the one thread, that ensure that the ALU instructions of the one thread that are dependent upon the elementary function unit instructions of the one thread follow the elementary function unit instructions of the one thread upon which the ALU instructions of the one thread depend. - View Dependent Claims (38, 39, 40, 41, 42, 43)
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Specification